}
 
 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
-static int intel_resume_prepare(struct drm_i915_private *dev_priv,
-                               bool rpm_resume);
+static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
+                             bool rpm_resume);
 
 static int i915_drm_suspend(struct drm_device *dev)
 {
 static int i915_drm_resume_early(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       int ret;
+       int ret = 0;
 
        /*
         * We have a resume ordering issue with the snd-hda driver also
 
        pci_set_master(dev->pdev);
 
-       ret = intel_resume_prepare(dev_priv, false);
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+               hsw_disable_pc8(dev_priv);
+       else if (IS_VALLEYVIEW(dev_priv))
+               ret = vlv_resume_prepare(dev_priv, false);
        if (ret)
                DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 
        return 0;
 }
 
-static int snb_resume_prepare(struct drm_i915_private *dev_priv,
-                               bool rpm_resume)
-{
-       struct drm_device *dev = dev_priv->dev;
-
-       if (rpm_resume)
-               intel_init_pch_refclk(dev);
-
-       return 0;
-}
-
-static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
-                               bool rpm_resume)
-{
-       hsw_disable_pc8(dev_priv);
-
-       return 0;
-}
-
 /*
  * Save all Gunit registers that may be lost after a D3 and a subsequent
  * S0i[R123] transition. The list of registers needing a save/restore is
        struct pci_dev *pdev = to_pci_dev(device);
        struct drm_device *dev = pci_get_drvdata(pdev);
        struct drm_i915_private *dev_priv = dev->dev_private;
-       int ret;
+       int ret = 0;
 
        if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
                return -ENODEV;
        intel_opregion_notify_adapter(dev, PCI_D0);
        dev_priv->pm.suspended = false;
 
-       ret = intel_resume_prepare(dev_priv, true);
+       if (IS_GEN6(dev_priv))
+               intel_init_pch_refclk(dev);
+       else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+               hsw_disable_pc8(dev_priv);
+       else if (IS_VALLEYVIEW(dev_priv))
+               ret = vlv_resume_prepare(dev_priv, true);
+
        /*
         * No point of rolling back things in case of an error, as the best
         * we can do is to hope that things will still work (and disable RPM).
        return ret;
 }
 
-/*
- * This function implements common functionality of runtime and system
- * resume sequence. Variable rpm_resume used for implementing different
- * code paths.
- */
-static int intel_resume_prepare(struct drm_i915_private *dev_priv,
-                               bool rpm_resume)
-{
-       struct drm_device *dev = dev_priv->dev;
-       int ret;
-
-       if (IS_GEN6(dev))
-               ret = snb_resume_prepare(dev_priv, rpm_resume);
-       else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-               ret = hsw_resume_prepare(dev_priv, rpm_resume);
-       else if (IS_VALLEYVIEW(dev))
-               ret = vlv_resume_prepare(dev_priv, rpm_resume);
-       else
-               ret = 0;
-
-       return ret;
-}
-
 static const struct dev_pm_ops i915_pm_ops = {
        /*
         * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,