PCI: microchip: Gather MSI information from hardware config registers

The PCIe Root Complex on PolarFire SoC is configured at bitstream creation
time using Libero. Key MSI-related parameters include the number of
MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract
this information from hardware registers at init time, and use it to configure
MSI system, including configuring MSI capability structure correctly in
configuration space.

Link: https://lore.kernel.org/r/20230728131401.1615724-7-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 7b212eea42d21babb4f35d347a8fae49671a30bc..ca13fd56a0d994f6185416a77a0aef7d58f0daf9 100644 (file)
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -7,6 +7,7 @@
  * Author: Daire McNamara <daire.mcnamara@microchip.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
@@ -20,8 +21,7 @@
 #include "../pci.h"
 
 /* Number of MSI IRQs */
-#define MC_NUM_MSI_IRQS                                32
-#define MC_NUM_MSI_IRQS_CODED                  5
+#define MC_MAX_NUM_MSI_IRQS                    32
 
 /* PCIe Bridge Phy and Controller Phy offsets */
 #define MC_PCIE1_BRIDGE_ADDR                   0x00008000u
@@ -31,6 +31,11 @@
 #define MC_PCIE_CTRL_ADDR                      (MC_PCIE1_CTRL_ADDR)
 
 /* PCIe Bridge Phy Regs */
+#define PCIE_PCI_IRQ_DW0                       0xa8
+#define  MSIX_CAP_MASK                         BIT(31)
+#define  NUM_MSI_MSGS_MASK                     GENMASK(6, 4)
+#define  NUM_MSI_MSGS_SHIFT                    4
+
 #define IMASK_LOCAL                            0x180
 #define  DMA_END_ENGINE_0_MASK                 0x00000000u
 #define  DMA_END_ENGINE_0_SHIFT                        0
@@ -79,7 +84,6 @@
 #define IMASK_HOST                             0x188
 #define ISTATUS_HOST                           0x18c
 #define IMSI_ADDR                              0x190
-#define  MSI_ADDR                              0x190
 #define ISTATUS_MSI                            0x194
 
 /* PCIe Master table init defines */
@@ -158,8 +162,6 @@
 
 /* PCIe Config space MSI capability structure */
 #define MC_MSI_CAP_CTRL_OFFSET                 0xe0u
-#define  MC_MSI_MAX_Q_AVAIL                    (MC_NUM_MSI_IRQS_CODED << 1)
-#define  MC_MSI_Q_SIZE                         (MC_NUM_MSI_IRQS_CODED << 4)
 
 /* Events */
 #define EVENT_PCIE_L2_EXIT                     0
@@ -259,7 +261,7 @@ struct mc_msi {
        struct irq_domain *dev_domain;
        u32 num_vectors;
        u64 vector_phy;
-       DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);
+       DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS);
 };
 
 struct mc_pcie {
@@ -382,25 +384,27 @@ static struct {
 
 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
 
-static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)
+static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)
 {
        struct mc_msi *msi = &port->msi;
-       u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;
-       u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);
+       u16 reg;
+       u8 queue_size;
 
-       msg_ctrl |= PCI_MSI_FLAGS_ENABLE;
-       msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;
-       msg_ctrl |= MC_MSI_MAX_Q_AVAIL;
-       msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
-       msg_ctrl |= MC_MSI_Q_SIZE;
-       msg_ctrl |= PCI_MSI_FLAGS_64BIT;
+       /* Fixup MSI enable flag */
+       reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
+       reg |= PCI_MSI_FLAGS_ENABLE;
+       writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
 
-       writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
+       /* Fixup PCI MSI queue flags */
+       queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg);
+       reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size);
+       writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
 
+       /* Fixup MSI addr fields */
        writel_relaxed(lower_32_bits(msi->vector_phy),
-                      base + cap_offset + PCI_MSI_ADDRESS_LO);
+                      ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO);
        writel_relaxed(upper_32_bits(msi->vector_phy),
-                      base + cap_offset + PCI_MSI_ADDRESS_HI);
+                      ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI);
 }
 
 static void mc_handle_msi(struct irq_desc *desc)
@@ -473,10 +477,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
 {
        struct mc_pcie *port = domain->host_data;
        struct mc_msi *msi = &port->msi;
-       void __iomem *bridge_base_addr =
-               port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
        unsigned long bit;
-       u32 val;
 
        mutex_lock(&msi->lock);
        bit = find_first_zero_bit(msi->used, msi->num_vectors);
@@ -490,11 +491,6 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
        irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,
                            domain->host_data, handle_edge_irq, NULL, NULL);
 
-       /* Enable MSI interrupts */
-       val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
-       val |= PM_MSI_INT_MSI_MASK;
-       writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
-
        mutex_unlock(&msi->lock);
 
        return 0;
@@ -1111,6 +1107,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
        struct mc_pcie *port;
        void __iomem *bridge_base_addr;
        int ret;
+       u32 val;
 
        port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
        if (!port)
@@ -1131,12 +1128,24 @@ static int mc_platform_init(struct pci_config_window *cfg)
 
        bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
 
-       port->msi.vector_phy = MSI_ADDR;
-       port->msi.num_vectors = MC_NUM_MSI_IRQS;
+       /* Allow enabling MSI by disabling MSI-X */
+       val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
+       val &= ~MSIX_CAP_MASK;
+       writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);
 
        /* Hardware doesn't setup MSI by default */
        mc_pcie_enable_msi(port, cfg->win);
 
+       /* Pick num vectors from bitfile programmed onto FPGA fabric */
+       val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
+       val &= NUM_MSI_MSGS_MASK;
+       val >>= NUM_MSI_MSGS_SHIFT;
+
+       port->msi.num_vectors = 1 << val;
+
+       /* Pick vector address from design */
+       port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);
+
        /* Configure Address Translation Table 0 for PCIe config space */
        mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
                             cfg->res.start, resource_size(&cfg->res));