clk: renesas: rcar-gen3: Add support for ZG clock

A clock used for the 3D graphics appears to be common
among multiple SoC's, so add a generic gen3 clock
for clocking the graphics.  This is similar to the
cpg_z_clk, with a different frequency control register
and different flags.  Instead of duplicating the code,
make cpg_z_clk_register into a helper function and
call the help function with the FCR and flags as
a parameter.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index b3ef62fa612e347e71f56414a3d1b75aef097e51..d0129a6509411662e04bdeb6bc3cfbcaee269885 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -264,11 +264,13 @@ static const struct clk_ops cpg_z_clk_ops = {
        .set_rate = cpg_z_clk_set_rate,
 };
 
-static struct clk * __init cpg_z_clk_register(const char *name,
+static struct clk * __init __cpg_z_clk_register(const char *name,
                                              const char *parent_name,
                                              void __iomem *reg,
                                              unsigned int div,
-                                             unsigned int offset)
+                                             unsigned int offset,
+                                             unsigned int fcr,
+                                             unsigned int flags)
 {
        struct clk_init_data init = {};
        struct cpg_z_clk *zclk;
@@ -280,11 +282,11 @@ static struct clk * __init cpg_z_clk_register(const char *name,
 
        init.name = name;
        init.ops = &cpg_z_clk_ops;
-       init.flags = CLK_SET_RATE_PARENT;
+       init.flags = flags;
        init.parent_names = &parent_name;
        init.num_parents = 1;
 
-       zclk->reg = reg + CPG_FRQCRC;
+       zclk->reg = reg + fcr;
        zclk->kick_reg = reg + CPG_FRQCRB;
        zclk->hw.init = &init;
        zclk->mask = GENMASK(offset + 4, offset);
@@ -301,6 +303,27 @@ static struct clk * __init cpg_z_clk_register(const char *name,
        return clk;
 }
 
+static struct clk * __init cpg_z_clk_register(const char *name,
+                                             const char *parent_name,
+                                             void __iomem *reg,
+                                             unsigned int div,
+                                             unsigned int offset)
+{
+       return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+                                   CPG_FRQCRC, CLK_SET_RATE_PARENT);
+}
+
+static struct clk * __init cpg_zg_clk_register(const char *name,
+                                              const char *parent_name,
+                                              void __iomem *reg,
+                                              unsigned int div,
+                                              unsigned int offset)
+{
+       return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+                                   CPG_FRQCRB, 0);
+
+}
+
 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
        { 2, 5 }, { 3, 6 }, { 0, 0 },
 };
@@ -438,6 +461,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
                return cpg_z_clk_register(core->name, __clk_get_name(parent),
                                          base, core->div, core->offset);
 
+       case CLK_TYPE_GEN3_ZG:
+               return cpg_zg_clk_register(core->name, __clk_get_name(parent),
+                                          base, core->div, core->offset);
+
        case CLK_TYPE_GEN3_OSC:
                /*
                 * Clock combining OSC EXTAL predivider and a fixed divider

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9028bf4295ce03d3dd7733b0fdaa5f920b22f999..bfdc649bdf12ca2ecade5d90ce450be69295ff63 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -22,6 +22,7 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_R,
        CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
        CLK_TYPE_GEN3_Z,
+       CLK_TYPE_GEN3_ZG,
        CLK_TYPE_GEN3_OSC,      /* OSC EXTAL predivider and fixed divider */
        CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
        CLK_TYPE_GEN3_RPCSRC,