arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
authorAndrew Davis <afd@ti.com>
Fri, 28 Oct 2022 14:24:09 +0000 (09:24 -0500)
committerNishanth Menon <nm@ti.com>
Fri, 4 Nov 2022 02:46:00 +0000 (21:46 -0500)
SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the SPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-4-afd@ti.com
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
arch/arm64/boot/dts/ti/k3-am654-base-board.dts

index 945a8a70332e9dd3fe8017ff7e3b0732212b26d7..fa4b6eb02fa576f40d27049f76eaf19c413212ea 100644 (file)
 };
 
 &mcu_spi0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_spi0_pins_default>;
 
index feef5fdb468862dda1992f00e14695ff968c6393..74fd807d473965a631d403b71d8aa55b1cc2cb39 100644 (file)
                #size-cells = <0>;
                dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
                dma-names = "tx0", "rx0";
+               status = "disabled";
        };
 
        main_spi1: spi@2110000 {
                #size-cells = <0>;
                assigned-clocks = <&k3_clks 137 1>;
                assigned-clock-rates = <48000000>;
+               status = "disabled";
        };
 
        main_spi2: spi@2120000 {
                power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        main_spi3: spi@2130000 {
                power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        main_spi4: spi@2140000 {
                power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        sdhci0: mmc@4f80000 {
index 56cb193d1741c66d44eaa95b99ef7892aa6ef276..ad7d27c943cc008daf470b0d87bb9f1cb3718bb8 100644 (file)
@@ -58,6 +58,7 @@
                power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        mcu_spi1: spi@40310000 {
@@ -68,6 +69,7 @@
                power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        mcu_spi2: spi@40320000 {
@@ -78,6 +80,7 @@
                power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
+               status = "disabled";
        };
 
        tscadc0: tscadc@40200000 {
index 991a8559b4c3b9331357819191d1904e4e68e43e..3f5a5ebfc8f3c5d9b0445dceea9ef9c9609c27b3 100644 (file)
 };
 
 &main_spi0 {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_spi0_pins_default>;
        #address-cells = <1>;