iwlwifi: mvm: add support for IMR based on platform
authorMukesh Sisodiya <mukesh.sisodiya@intel.com>
Fri, 4 Mar 2022 11:21:22 +0000 (13:21 +0200)
committerLuca Coelho <luciano.coelho@intel.com>
Thu, 10 Mar 2022 07:23:27 +0000 (09:23 +0200)
Driver needs to enable IMR which is needed for debug on
certain platforms, so add a device config flag to set it.

Signed-off-by: Mukesh Sisodiya <mukesh.sisodiya@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20220304131517.0b96b2760503.I08bc741c8c497a2edbe4784cdab6abd8d04c62f3@changeid
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
drivers/net/wireless/intel/iwlwifi/cfg/22000.c
drivers/net/wireless/intel/iwlwifi/iwl-config.h
drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c
drivers/net/wireless/intel/iwlwifi/pcie/drv.c

index a0c777914e38c5bc600984938071d3aec57a8fbb..8afd5e16e5d85a5a06be482b7022e2bf6a63e6fb 100644 (file)
@@ -391,6 +391,21 @@ const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
        .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 };
 
+const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
+       .mq_rx_supported = true,
+       .use_tfh = true,
+       .rf_id = true,
+       .gen2 = true,
+       .device_family = IWL_DEVICE_FAMILY_AX210,
+       .base_params = &iwl_ax210_base_params,
+       .umac_prph_offset = 0x300000,
+       .integrated = true,
+       .low_latency_xtal = true,
+       .xtal_latency = 12000,
+       .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
+       .imr_enabled = true,
+};
+
 /*
  * If the device doesn't support HE, no need to have that many buffers.
  * 22000 devices can split multiple frames into a single RB, so fewer are
index b7e430ad5e2a608df77223b10ab122cffedcceed..f5b556a103e8ce01c0000afd606357c3fe3f6412 100644 (file)
@@ -260,6 +260,7 @@ enum iwl_cfg_trans_ltr_delay {
  * @integrated: discrete or integrated
  * @low_latency_xtal: use the low latency xtal if supported
  * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
+ * @imr_enabled: use the IMR if supported.
  */
 struct iwl_cfg_trans_params {
        const struct iwl_base_params *base_params;
@@ -274,7 +275,8 @@ struct iwl_cfg_trans_params {
            integrated:1,
            low_latency_xtal:1,
            bisr_workaround:1,
-           ltr_delay:2;
+           ltr_delay:2,
+           imr_enabled:1;
 };
 
 /**
@@ -491,6 +493,7 @@ extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
 extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg;
 extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
 extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
+extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
 extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
 extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
 extern const char iwl9162_name[];
index 5adf485db38e206a08ec5bd350218986c2b7c5a3..b84884034c74772f1ef3c6a9882da4c064272750 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2018, 2020-2021 Intel Corporation
+ * Copyright (C) 2018, 2020-2022 Intel Corporation
  */
 #ifndef __iwl_context_info_file_gen3_h__
 #define __iwl_context_info_file_gen3_h__
@@ -34,6 +34,7 @@ enum iwl_prph_scratch_mtr_format {
 
 /**
  * enum iwl_prph_scratch_flags - PRPH scratch control flags
+ * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
  * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
  * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
  *     in hwm config.
@@ -55,6 +56,7 @@ enum iwl_prph_scratch_mtr_format {
  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
  */
 enum iwl_prph_scratch_flags {
+       IWL_PRPH_SCRATCH_IMR_DEBUG_EN           = BIT(1),
        IWL_PRPH_SCRATCH_EARLY_DEBUG_EN         = BIT(4),
        IWL_PRPH_SCRATCH_EDBG_DEST_DRAM         = BIT(8),
        IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL     = BIT(9),
index 85a6da70ca787bd3fc722028f167e196f87ffe9a..75fd386b048e9ba6308ae2a0ed3cd6e1be0a7998 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
  */
 #include "iwl-trans.h"
 #include "iwl-fh.h"
@@ -125,6 +125,9 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
        control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
        control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
 
+       if (trans->trans_cfg->imr_enabled)
+               control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN;
+
        /* initialize RX default queue */
        prph_sc_ctrl->rbd_cfg.free_rbd_addr =
                cpu_to_le64(trans_pcie->rxq->bd_dma);
index 58a7111d4f406cf1f93a9462672d8155b354d5b5..b16d4ae182d10b179094ae7d155c124129a649c4 100644 (file)
@@ -491,9 +491,10 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
 /* So devices */
        {IWL_PCI_DEVICE(0x2725, PCI_ANY_ID, iwl_so_trans_cfg)},
        {IWL_PCI_DEVICE(0x2726, PCI_ANY_ID, iwl_snj_trans_cfg)},
-       {IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
+       {IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
        {IWL_PCI_DEVICE(0x7AF0, PCI_ANY_ID, iwl_so_trans_cfg)},
        {IWL_PCI_DEVICE(0x51F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
+       {IWL_PCI_DEVICE(0x51F1, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
        {IWL_PCI_DEVICE(0x54F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
        {IWL_PCI_DEVICE(0x7F70, PCI_ANY_ID, iwl_so_trans_cfg)},