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riscv: dts: add reset generator for Sophgo SG2042 SoC
author
Chen Wang
<unicorn_wang@outlook.com>
Tue, 30 Jan 2024 01:50:32 +0000
(09:50 +0800)
committer
Inochi Amaoto
<inochiama@outlook.com>
Fri, 23 Feb 2024 04:38:03 +0000
(12:38 +0800)
Add reset generator node to device tree for SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Link:
https://lore.kernel.org/r/b2f5d7cd2d3fccfc00cf4563d2dd7363b0fa2fca.1706577450.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
arch/riscv/boot/dts/sophgo/sg2042.dtsi
patch
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diff --git
a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index ead1cc35d88b2f13bfecf935a6e66e6049a24a75..eeb341e16bfd68683fc89e33f01e029b1b4253a0 100644
(file)
--- a/
arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/
arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@
-6,6
+6,8
@@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sophgo,sg2042-reset.h>
+
#include "sg2042-cpus.dtsi"
/ {
@@
-327,6
+329,12
@@
riscv,ndev = <224>;
};
+ rstgen: reset-controller@7030013000 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;