case CNFG_MEMSIZE:
val = s->vga.vram_size;
break;
+ case CONFIG_APER_0_BASE:
+ case CONFIG_APER_1_BASE:
+ val = pci_default_read_config(&s->dev,
+ PCI_BASE_ADDRESS_0, size) & 0xfffffff0;
+ break;
+ case CONFIG_APER_SIZE:
+ val = s->vga.vram_size;
+ break;
+ case CONFIG_REG_1_BASE:
+ val = pci_default_read_config(&s->dev,
+ PCI_BASE_ADDRESS_2, size) & 0xfffffff0;
+ break;
+ case CONFIG_REG_APER_SIZE:
+ val = memory_region_size(&s->mm);
+ break;
case MC_STATUS:
val = 5;
break;
{"CNFG_CNTL", 0x00e0},
{"GEN_RESET_CNTL", 0x00f0},
{"CNFG_MEMSIZE", 0x00f8},
+ {"CONFIG_APER_0_BASE", 0x0100},
+ {"CONFIG_APER_1_BASE", 0x0104},
+ {"CONFIG_APER_SIZE", 0x0108},
+ {"CONFIG_REG_1_BASE", 0x010c},
+ {"CONFIG_REG_APER_SIZE", 0x0110},
{"MEM_CNTL", 0x0140},
{"MC_FB_LOCATION", 0x0148},
{"MC_AGP_LOCATION", 0x014C},
#define CNFG_CNTL 0x00e0
#define GEN_RESET_CNTL 0x00f0
#define CNFG_MEMSIZE 0x00f8
+#define CONFIG_APER_0_BASE 0x0100
+#define CONFIG_APER_1_BASE 0x0104
+#define CONFIG_APER_SIZE 0x0108
+#define CONFIG_REG_1_BASE 0x010c
+#define CONFIG_REG_APER_SIZE 0x0110
#define MEM_CNTL 0x0140
#define MC_FB_LOCATION 0x0148
#define MC_AGP_LOCATION 0x014C