ARM: dts: rockchip: restyle emac nodes
authorJohan Jonker <jbx6244@gmail.com>
Fri, 3 Jun 2022 16:35:39 +0000 (18:35 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Fri, 9 Sep 2022 22:58:36 +0000 (00:58 +0200)
The emac_rockchip.txt file is converted to YAML.
Phy nodes are now a subnode of mdio, so restyle
the emac nodes of rk3036/rk3066/rk3188.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220603163539.537-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3036-evb.dts
arch/arm/boot/dts/rk3036-kylin.dts
arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/rk3066a-marsboard.dts
arch/arm/boot/dts/rk3066a-rayeager.dts
arch/arm/boot/dts/rk3188-radxarock.dts
arch/arm/boot/dts/rk3xxx.dtsi

index 2a7e6624efb93127ab3167bad028b21dab33ad2a..9fd4d9db9f8f67c665eefd4bc12fbb96b2f3f21e 100644 (file)
 };
 
 &emac {
-       pinctrl-names = "default";
-       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
        phy = <&phy0>;
-       phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
        phy-reset-duration = <10>; /* millisecond */
-
+       phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
        status = "okay";
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
        };
 };
 
index e817eba8c622baa025c5ef1d0477953bb7201480..67e1e04139e7326bc2539d555dd2be10fec1d146 100644 (file)
 };
 
 &emac {
-       pinctrl-names = "default";
-       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
        phy = <&phy0>;
-       phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
        phy-reset-duration = <10>; /* millisecond */
-
+       phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
        status = "okay";
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
        };
 };
 
index e240b89b0b35267131b9d0dcc1e10051836e10c9..78686fc72ce69ac140049e328c5d35123486f57c 100644 (file)
                compatible = "rockchip,rk3036-emac";
                reg = <0x10200000 0x4000>;
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-               #address-cells = <1>;
-               #size-cells = <0>;
                rockchip,grf = <&grf>;
                clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
                clock-names = "hclk", "macref", "macclk";
index a66d915aa0f65758f1e733cb70ce44bad5de7d77..8beecd628282412621b89c237cc10af8668c07fd 100644 (file)
 #include "tps65910.dtsi"
 
 &emac {
-       status = "okay";
-
        phy = <&phy0>;
        phy-supply = <&vcc_rmii>;
-
        pinctrl-names = "default";
        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               interrupt-parent = <&gpio1>;
-               interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               };
        };
 };
 
index dbbc5170094e01ffc6a91b52322cc2564ae094d6..3eee42137b6da8bf70ace489ce5c3dd758bfc8fc 100644 (file)
 };
 
 &emac {
-       pinctrl-names = "default";
-       pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
        phy = <&phy0>;
        phy-supply = <&vcc_rmii>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
        status = "okay";
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 
index a9ed3cd2c2da64512a557a58af7753f300286fea..e7cf18823558abb2c438176d0528cdf07555f393 100644 (file)
 };
 
 &emac {
-       status = "okay";
-
+       phy = <&phy0>;
+       phy-supply = <&vcc_rmii>;
        pinctrl-names = "default";
        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+       status = "okay";
 
-       phy = <&phy0>;
-       phy-supply = <&vcc_rmii>;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               interrupt-parent = <&gpio3>;
-               interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       interrupt-parent = <&gpio3>;
+                       interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               };
        };
 };
 
index 616a828e0c6e4c6f58588798d0c019767e0754a1..bf285091a9eb11b15d527218051043a726cd8dad 100644 (file)
                compatible = "snps,arc-emac";
                reg = <0x10204000 0x3c>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                rockchip,grf = <&grf>;