drm/amdgpu: use psp_execute_load_ip_fw instead
authorLang Yu <Lang.Yu@amd.com>
Sat, 8 Jul 2023 04:43:14 +0000 (12:43 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 12 Jul 2023 15:12:09 +0000 (11:12 -0400)
Replace the old ones with psp_execute_load_ip_fw.

Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

index a1a4408e524dfc818d60d2ebd962f52f57e8597b..1b4d5f04d968e5bc0a118ca294348ff73e151784 100644 (file)
@@ -2920,19 +2920,6 @@ int psp_rlc_autoload_start(struct psp_context *psp)
        return ret;
 }
 
-int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
-                       uint64_t cmd_gpu_addr, int cmd_size)
-{
-       struct amdgpu_firmware_info ucode = {0};
-
-       ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
-               AMDGPU_UCODE_ID_VCN0_RAM;
-       ucode.mc_addr = cmd_gpu_addr;
-       ucode.ucode_size = cmd_size;
-
-       return psp_execute_ip_fw_load(&adev->psp, &ucode);
-}
-
 int psp_ring_cmd_submit(struct psp_context *psp,
                        uint64_t cmd_buf_mc_addr,
                        uint64_t fence_mc_addr,
index efb3972bfebdbef3cdfbccf250027b06435c1424..c3203de4a0078ff2f3cd8983e6256b4280102289 100644 (file)
@@ -466,8 +466,6 @@ int psp_execute_ip_fw_load(struct psp_context *psp,
                           struct amdgpu_firmware_info *ucode);
 
 int psp_gpu_reset(struct amdgpu_device *adev);
-int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
-                       uint64_t cmd_gpu_addr, int cmd_size);
 
 int psp_ta_init_shared_buf(struct psp_context *psp,
                                  struct ta_mem_context *mem_ctx);
index ae455aab5d29ddfd154e0533796b88b96cdfc98a..36b55d2bd51a91fa52986cba5831b73bb102632c 100644 (file)
@@ -1239,3 +1239,18 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
 
        return 0;
 }
+
+int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
+                              enum AMDGPU_UCODE_ID ucode_id)
+{
+       struct amdgpu_firmware_info ucode = {
+               .ucode_id = (ucode_id ? ucode_id :
+                           (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
+                                       AMDGPU_UCODE_ID_VCN0_RAM)),
+               .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
+               .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
+                             (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
+       };
+
+       return psp_execute_ip_fw_load(&adev->psp, &ucode);
+}
index 92d5534df5f42848b2a5f8f49b3298fd8c399137..1f1d7dc94f90939578672df1dacd2c2eed56486c 100644 (file)
@@ -414,4 +414,7 @@ int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,
                        struct ras_common_if *ras_block);
 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
 
+int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
+                              enum AMDGPU_UCODE_ID ucode_id);
+
 #endif
index c975aed2f6c7845f480e0a9b17db92a7110ba217..18794394c5a052b26ef009647616a8aba92efd9a 100644 (file)
@@ -881,9 +881,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
        if (indirect)
-               psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
-                                   (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
-                                              (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
+               amdgpu_vcn_psp_update_sram(adev, 0, 0);
 
        /* force RBC into idle state */
        rb_bufsz = order_base_2(ring->ring_size);
index bb1875f926f19d78d16a08538df7232ed0f1c5be..6fbea38f4d3e1bd3caeddcff9527f47c281adfc5 100644 (file)
@@ -912,9 +912,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
        if (indirect)
-               psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
-                                   (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
-                                              (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
+               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
 
        ring = &adev->vcn.inst[inst_idx].ring_dec;
        /* force RBC into idle state */
index c8f63b3c6f69d945388187d41c65482686e3b354..b76ba21b5a896c9a5ca8614c73b685064527b0ff 100644 (file)
@@ -1037,9 +1037,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
                VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 
        if (indirect)
-               psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
-                       (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
-                               (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
+               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
 
        ring = &adev->vcn.inst[inst_idx].ring_dec;
        /* force RBC into idle state */
index 259795098173ac5cb7800959536bb51e1342abeb..5dc135520897e304ecf6b6481de5e5645d576ab0 100644 (file)
@@ -993,9 +993,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 
 
        if (indirect)
-               psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
-                       (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
-                               (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
+               amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
index 5d67b8b8a3d6bc03a566c62dd56cb9b785df3dc7..550ac040b4be85b06af2bebe5d556ea413fc5645 100644 (file)
@@ -778,9 +778,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
                UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 
        if (indirect)
-               psp_update_vcn_sram(adev, 0, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
-                       (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
-                               (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
+               amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
 
        ring = &adev->vcn.inst[inst_idx].ring_enc[0];