clk: qcom: Add LUCID_OLE PLL type for SM8550

Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130112852.2977816-5-abel.vesa@linaro.org

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 1973d79c94655225105cc341653e4b060dac0730..f9e4cfd7261c1f97e8c13042e0670ab22880f9ea 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -155,6 +155,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                [PLL_OFF_TEST_CTL_U] = 0x30,
                [PLL_OFF_TEST_CTL_U1] = 0x34,
        },
+       [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
+               [PLL_OFF_OPMODE] = 0x04,
+               [PLL_OFF_STATE] = 0x08,
+               [PLL_OFF_STATUS] = 0x0c,
+               [PLL_OFF_L_VAL] = 0x10,
+               [PLL_OFF_ALPHA_VAL] = 0x14,
+               [PLL_OFF_USER_CTL] = 0x18,
+               [PLL_OFF_USER_CTL_U] = 0x1c,
+               [PLL_OFF_CONFIG_CTL] = 0x20,
+               [PLL_OFF_CONFIG_CTL_U] = 0x24,
+               [PLL_OFF_CONFIG_CTL_U1] = 0x28,
+               [PLL_OFF_TEST_CTL] = 0x2c,
+               [PLL_OFF_TEST_CTL_U] = 0x30,
+               [PLL_OFF_TEST_CTL_U1] = 0x34,
+               [PLL_OFF_TEST_CTL_U2] = 0x38,
+       },
        [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
                [PLL_OFF_OPMODE] = 0x04,
                [PLL_OFF_STATUS] = 0x0c,

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index f9524b3fce6b9f21efbc87ca39afc04dd233dee0..2bdae362c827845edda702ff86e021d85f40fedd 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -18,6 +18,7 @@ enum {
        CLK_ALPHA_PLL_TYPE_AGERA,
        CLK_ALPHA_PLL_TYPE_ZONDA,
        CLK_ALPHA_PLL_TYPE_LUCID_EVO,
+       CLK_ALPHA_PLL_TYPE_LUCID_OLE,
        CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
        CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
        CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
@@ -38,6 +39,8 @@ enum {
        PLL_OFF_TEST_CTL,
        PLL_OFF_TEST_CTL_U,
        PLL_OFF_TEST_CTL_U1,
+       PLL_OFF_TEST_CTL_U2,
+       PLL_OFF_STATE,
        PLL_OFF_STATUS,
        PLL_OFF_OPMODE,
        PLL_OFF_FRAC,
@@ -160,7 +163,9 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
+#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
+#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
 
 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops