firmware: xilinx: Add qspi firmware interface
authorRajan Vaja <rajan.vaja@xilinx.com>
Tue, 11 Oct 2022 06:20:37 +0000 (11:50 +0530)
committerMark Brown <broonie@kernel.org>
Wed, 19 Oct 2022 13:34:37 +0000 (14:34 +0100)
Add support for QSPI ioctl functions and enums.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Link: https://lore.kernel.org/r/20221011062040.12116-5-amit.kumar-mahapatra@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/firmware/xilinx/zynqmp.c
include/linux/firmware/xlnx-zynqmp.h

index ff5cabe70a2b2478eef8b742149546d03cc57daf..6bc6b6c84241ca940a938339b567ab142e7e3221 100644 (file)
@@ -843,6 +843,13 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
 
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+       return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
+                                  index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
+
 /**
  * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
  * @value:     Status value to be written
index 76d2b3ebad8477a962dd2fc37f14509a09b2246a..fac37680ffe7b2d6ee1935db012665b0eb060614 100644 (file)
@@ -135,6 +135,7 @@ enum pm_ret_status {
 };
 
 enum pm_ioctl_id {
+       IOCTL_SET_TAPDELAY_BYPASS = 4,
        IOCTL_SD_DLL_RESET = 6,
        IOCTL_SET_SD_TAPDELAY = 7,
        IOCTL_SET_PLL_FRAC_MODE = 8,
@@ -389,6 +390,18 @@ enum zynqmp_pm_shutdown_subtype {
        ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 };
 
+enum tap_delay_signal_type {
+       PM_TAPDELAY_NAND_DQS_IN = 0,
+       PM_TAPDELAY_NAND_DQS_OUT = 1,
+       PM_TAPDELAY_QSPI = 2,
+       PM_TAPDELAY_MAX = 3,
+};
+
+enum tap_delay_bypass_ctrl {
+       PM_TAPDELAY_BYPASS_DISABLE = 0,
+       PM_TAPDELAY_BYPASS_ENABLE = 1,
+};
+
 enum ospi_mux_select_type {
        PM_OSPI_MUX_SEL_DMA = 0,
        PM_OSPI_MUX_SEL_LINEAR = 1,
@@ -484,6 +497,7 @@ int zynqmp_pm_write_ggs(u32 index, u32 value);
 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 int zynqmp_pm_write_pggs(u32 index, u32 value);
 int zynqmp_pm_read_pggs(u32 index, u32 *value);
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 int zynqmp_pm_set_boot_health_status(u32 value);
 int zynqmp_pm_pinctrl_request(const u32 pin);
@@ -696,6 +710,11 @@ static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
        return -ENODEV;
 }
 
+static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+       return -ENODEV;
+}
+
 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 {
        return -ENODEV;