drm/amdgpu/pm: properly handle sclk for profiling modes on vangogh

[ Upstream commit 68e3871dcd6e547f6c47454492bc452356cb9eac ]

When selecting between levels in the force performance levels interface
sclk (gfxclk) was not set correctly for all levels.  Select the proper
sclk settings for all levels.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1726
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index f6ef0ce6e9e2c30e509df6c6e077b02fa3af7f29..a9dceef4a7011155beaca31e42ceac04040dc820 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1386,52 +1386,38 @@ static int vangogh_set_performance_level(struct smu_context *smu,
        uint32_t soc_mask, mclk_mask, fclk_mask;
        uint32_t vclk_mask = 0, dclk_mask = 0;
 
+       smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+       smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
        switch (level) {
        case AMD_DPM_FORCED_LEVEL_HIGH:
-               smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+               smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
                smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
 
                ret = vangogh_force_dpm_limit_value(smu, true);
+               if (ret)
+                       return ret;
                break;
        case AMD_DPM_FORCED_LEVEL_LOW:
                smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
-               smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
-
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+               smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
 
                ret = vangogh_force_dpm_limit_value(smu, false);
+               if (ret)
+                       return ret;
                break;
        case AMD_DPM_FORCED_LEVEL_AUTO:
                smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
                smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
-
                ret = vangogh_unforce_dpm_levels(smu);
-               break;
-       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
-               smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
-               smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
-
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
-
-               ret = smu_cmn_send_smc_msg_with_param(smu,
-                                       SMU_MSG_SetHardMinGfxClk,
-                                       VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
-               if (ret)
-                       return ret;
-
-               ret = smu_cmn_send_smc_msg_with_param(smu,
-                                       SMU_MSG_SetSoftMaxGfxClk,
-                                       VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
                if (ret)
                        return ret;
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+               smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
+               smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
 
                ret = vangogh_get_profiling_clk_mask(smu, level,
                                                        &vclk_mask,
@@ -1446,32 +1432,15 @@ static int vangogh_set_performance_level(struct smu_context *smu,
                vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
                vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
                vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
-
                break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
                smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
-               smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
-
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
-
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
-                                                               VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
-               if (ret)
-                       return ret;
-
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn,
-                                                               VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
-               if (ret)
-                       return ret;
+               smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
                break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
                smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
                smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
-
                ret = vangogh_get_profiling_clk_mask(smu, level,
                                                        NULL,
                                                        NULL,
@@ -1484,29 +1453,29 @@ static int vangogh_set_performance_level(struct smu_context *smu,
                vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
                break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-               smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
-               smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
-
-               smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
-               smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
-
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
-                               VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
-               if (ret)
-                       return ret;
+               smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
+               smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
 
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
-                               VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
+               ret = vangogh_set_peak_clock_by_device(smu);
                if (ret)
                        return ret;
-
-               ret = vangogh_set_peak_clock_by_device(smu);
                break;
        case AMD_DPM_FORCED_LEVEL_MANUAL:
        case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
        default:
-               break;
+               return 0;
        }
+
+       ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
+                                             smu->gfx_actual_hard_min_freq, NULL);
+       if (ret)
+               return ret;
+
+       ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
+                                             smu->gfx_actual_soft_max_freq, NULL);
+       if (ret)
+               return ret;
+
        return ret;
 }