drm/amdgpu: remove ras_error_status parameter for UMC poison handler
authorTao Zhou <tao.zhou1@amd.com>
Tue, 18 Oct 2022 02:31:09 +0000 (10:31 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Oct 2022 19:12:08 +0000 (15:12 -0400)
Make the code simpler.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

index 0561812aa0a43ed07362c4627098673c4f623c6b..37db39ba8718c06aace56ad5575b702585787bb8 100644 (file)
@@ -753,9 +753,7 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
 
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
 {
-       struct ras_err_data err_data = {0, 0, 0, NULL};
-
-       amdgpu_umc_poison_handler(adev, &err_data, reset);
+       amdgpu_umc_poison_handler(adev, reset);
 }
 
 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
index 28463b47ce33347d12e8b66a3e4a7c56e62be182..693bce07eb46423c631437224829f1ad6741b67d 100644 (file)
@@ -1561,7 +1561,6 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
 {
        bool poison_stat = false;
        struct amdgpu_device *adev = obj->adev;
-       struct ras_err_data err_data = {0, 0, 0, NULL};
        struct amdgpu_ras_block_object *block_obj =
                amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
 
@@ -1584,7 +1583,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
        }
 
        if (!adev->gmc.xgmi.connected_to_cpu)
-               amdgpu_umc_poison_handler(adev, &err_data, false);
+               amdgpu_umc_poison_handler(adev, false);
 
        if (block_obj->hw_ops->handle_poison_consumption)
                poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
index 758942150c0972a7bb5245df7736500a33c2b24e..f76c19fc03926fb5c77fba1e9c940e114134acc5 100644 (file)
@@ -165,25 +165,22 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
        return AMDGPU_RAS_SUCCESS;
 }
 
-int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
-               void *ras_error_status,
-               bool reset)
+int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset)
 {
        int ret = AMDGPU_RAS_SUCCESS;
 
        if (!adev->gmc.xgmi.connected_to_cpu) {
-               struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+               struct ras_err_data err_data = {0, 0, 0, NULL};
                struct ras_common_if head = {
                        .block = AMDGPU_RAS_BLOCK__UMC,
                };
                struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
 
-               ret =
-                       amdgpu_umc_do_page_retirement(adev, ras_error_status, NULL, reset);
+               ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
 
                if (ret == AMDGPU_RAS_SUCCESS && obj) {
-                       obj->err_data.ue_count += err_data->ue_count;
-                       obj->err_data.ce_count += err_data->ce_count;
+                       obj->err_data.ue_count += err_data.ue_count;
+                       obj->err_data.ce_count += err_data.ce_count;
                }
        } else if (reset) {
                /* MCA poison handler is only responsible for GPU reset,
index 659a10de29c95d2d6fce6b46bbd93beac5a94d84..a6951160f13af64c37c9033cc6513034cb1cf35d 100644 (file)
@@ -83,9 +83,7 @@ struct amdgpu_umc {
 };
 
 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
-               void *ras_error_status,
-               bool reset);
+int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset);
 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
                struct amdgpu_irq_src *source,
                struct amdgpu_iv_entry *entry);