clk: renesas: r8a77995: Fix VIN parent clock

According to the R-Car Series, 3rd Generation Hardware User’s Manual
Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3
is S3D1.  Update the driver to match the documentation.

This has no functional impact, as both S1D2 and S3D1 have the same clock
rate, and are always-on clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/9b655843a260e06fa6f3349cdafac180e2bf38a5.1676368776.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 24ba9093a72f7341ab79c27182732cbf60ad1f9c..3a73f6f911dd5160f1ee6116b522b24f0f6d1875 100644 (file)
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
        DEF_MOD("du0",                   724,   R8A77995_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
        DEF_MOD("mlp",                   802,   R8A77995_CLK_S2D1),
-       DEF_MOD("vin4",                  807,   R8A77995_CLK_S1D2),
+       DEF_MOD("vin4",                  807,   R8A77995_CLK_S3D1),
        DEF_MOD("etheravb",              812,   R8A77995_CLK_S3D2),
        DEF_MOD("imr0",                  823,   R8A77995_CLK_S1D2),
        DEF_MOD("gpio6",                 906,   R8A77995_CLK_S3D4),