arm64: dts: ti: k3-j721s2: Change CPTS clock parent

MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as their parent which does not have this flag. While RGMII
needs this reinitialisation to default frequency to be able to get
250MHz with its divider, CPTS can not get its required 200MHz with its
divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6.

(Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
for the same reason)

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 12a5b7008aca53f4e29dcc3bdd18346890a625dc..ed79ab3a32718f7d55e9c288441ea2e9cbb519a7 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1030,6 +1030,8 @@
                        reg-names = "cpts";
                        clocks = <&k3_clks 226 5>;
                        clock-names = "cpts";
+                       assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
+                       assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
                        interrupts-extended = <&main_navss_intr 391>;
                        interrupt-names = "cpts";
                        ti,cpts-periodic-outputs = <6>;

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 939cd037a814e0034d8c69acd0416cc718851d3b..5734c67b6763da9a1a5d18e7084c0e88bba5439f 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -525,6 +525,8 @@
                        reg = <0x0 0x3d000 0x0 0x400>;
                        clocks = <&k3_clks 29 3>;
                        clock-names = "cpts";
+                       assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
+                       assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
                        interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "cpts";
                        ti,cpts-ext-ts-inputs = <4>;