};
 
 /* Define Host controllers for Intel Merrifield platform */
-#define INTEL_MRFL_EMMC_0      0
-#define INTEL_MRFL_EMMC_1      1
+#define INTEL_MRFLD_EMMC_0     0
+#define INTEL_MRFLD_EMMC_1     1
 
-static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
+static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
 {
-       if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
-           (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
+       if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_0) &&
+           (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_1))
                /* SD support is not ready yet */
                return -ENODEV;
 
        return 0;
 }
 
-static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
+static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
        .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
        .quirks2        = SDHCI_QUIRK2_BROKEN_HS200 |
                        SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
        .allow_runtime_pm = true,
-       .probe_slot     = intel_mrfl_mmc_probe_slot,
+       .probe_slot     = intel_mrfld_mmc_probe_slot,
 };
 
 /* O2Micro extra registers */
 
        {
                .vendor         = PCI_VENDOR_ID_INTEL,
-               .device         = PCI_DEVICE_ID_INTEL_MRFL_MMC,
+               .device         = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
                .subvendor      = PCI_ANY_ID,
                .subdevice      = PCI_ANY_ID,
-               .driver_data    = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
+               .driver_data    = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
        },
 
        {
 
 #define PCI_DEVICE_ID_INTEL_BSW_EMMC   0x2294
 #define PCI_DEVICE_ID_INTEL_BSW_SDIO   0x2295
 #define PCI_DEVICE_ID_INTEL_BSW_SD     0x2296
-#define PCI_DEVICE_ID_INTEL_MRFL_MMC   0x1190
+#define PCI_DEVICE_ID_INTEL_MRFLD_MMC  0x1190
 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0  0x08f9
 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1  0x08fa
 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2  0x08fb