wifi: rt2x00: improve MT7620 register initialization
authorShiji Yang <yangshiji66@outlook.com>
Thu, 19 Oct 2023 11:58:56 +0000 (19:58 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 25 Oct 2023 09:06:15 +0000 (12:06 +0300)
1. Do not hard reset the BBP. We can use soft reset instead. This
   change has some help to the calibration failure issue.
2. Enable falling back to legacy rate from the HT/RTS rate by
   setting the HT_FBK_TO_LEGACY register.
3. Implement MCS rate specific maximum PSDU size. It can improve
   the transmission quality under the low RSSI condition.
4. Set BBP_84 register value to 0x19. This is used for extension
   channel overlapping IOT.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/TYAP286MB031553CCD4B7A3B89C85935DBCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
drivers/net/wireless/ralink/rt2x00/rt2800.h
drivers/net/wireless/ralink/rt2x00/rt2800lib.c
drivers/net/wireless/ralink/rt2x00/rt2800mmio.c

index de2ee5ffc34e7bd335f7c67fde912afa66dbae8c..48521e45577de4835ab5fbd99b2213017d06f1e5 100644 (file)
 #define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
 #define LED_CFG_LED_POLAR              FIELD32(0x40000000)
 
+/*
+ * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7
+ * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15
+ * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7
+ * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15
+ * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes
+ */
+#define AMPDU_MAX_LEN_20M1S            0x1030
+#define AMPDU_MAX_LEN_20M2S            0x1034
+#define AMPDU_MAX_LEN_40M1S            0x1038
+#define AMPDU_MAX_LEN_40M2S            0x103C
+
 /*
  * AMPDU_BA_WINSIZE: Force BlockAck window size
  * FORCE_WINSIZE_ENABLE:
  */
 #define EXP_ACK_TIME                   0x1380
 
+/*
+ * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate
+ * Not available for legacy SoCs
+ */
+#define HT_FBK_TO_LEGACY               0x1384
+
 /* TX_PWR_CFG_5 */
 #define TX_PWR_CFG_5                   0x1384
 #define TX_PWR_CFG_5_MCS16_CH0         FIELD32(0x0000000f)
index b93cfcb1e257bd3396127e7092a1c954a9653435..524ea2583d492f4a5d8bc7f071c1be083686a2d8 100644 (file)
@@ -5851,6 +5851,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
        struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
        u32 reg;
        u16 eeprom;
+       u8 bbp;
        unsigned int i;
        int ret;
 
@@ -5860,6 +5861,19 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
        if (ret)
                return ret;
 
+       if (rt2x00_rt(rt2x00dev, RT6352)) {
+               rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);
+
+               bbp = rt2800_bbp_read(rt2x00dev, 21);
+               bbp |= 0x01;
+               rt2800_bbp_write(rt2x00dev, 21, bbp);
+               bbp = rt2800_bbp_read(rt2x00dev, 21);
+               bbp &= (~0x01);
+               rt2800_bbp_write(rt2x00dev, 21, bbp);
+
+               rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
+       }
+
        rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
        rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 
@@ -6013,6 +6027,14 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
                rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
                rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
+
+               rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);
+               rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);
+               rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);
+               rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);
+
+               rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);
+
        } else {
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -7231,6 +7253,8 @@ static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
        rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
 
        rt2800_bbp4_mac_if_ctrl(rt2x00dev);
+
+       rt2800_bbp_write(rt2x00dev, 84, 0x19);
 }
 
 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
index 862098f753d24bb878dc52a7a26f6f7df5a50987..5323acff962a38c9f9b65a0a92880b1376f4a719 100644 (file)
@@ -760,6 +760,9 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
 
        rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 
+       if (rt2x00_rt(rt2x00dev, RT6352))
+               return 0;
+
        reg = 0;
        rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
        rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);