drm/i915/gt: Move engine registers to their own header

Let's continue breaking up and cleaning up the massive i915_reg.h file
by moving all registers that are defined in relation to an engine base
to their own header.

There are probably a bunch of other "engine registers" that we haven't
moved yet (especially those that belong to the render engine in the
0x2??? range), but this is a relatively straightforward first step.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-8-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 61383830505e95e055aa4fae133c8f810b287691..e0e8d228b31fce788687d87358c43bf2b959af85 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -6,6 +6,7 @@
 #include "gen2_engine_cs.h"
 #include "i915_drv.h"
 #include "intel_engine.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"

diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index b388ceeeb1c9b63a4f850c1e8a5126cf79f1df6d..5e65550b4dfb440beee0f7174c3b10b5f6f36c05 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -5,6 +5,7 @@
 
 #include "gen6_engine_cs.h"
 #include "intel_engine.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"

diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 890191f286e382b46a4bad33ea7c982007b3efe8..bc995f41058d68ffed0dca8c4d12a70453f261c6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -9,6 +9,7 @@
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
 #include "i915_vgpu.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 
 /* Write pde (index) from the page directory @pd to the page table @pt */

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0ad1f594f63607b2e8fa7e6b0710b582f6dc0fb8..d70fc19ec60b46b03bdbbd31ba57b4c389d576d2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -13,6 +13,7 @@
 #include "intel_context.h"
 #include "intel_engine.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_engine_user.h"
 #include "intel_execlists_submission.h"
 #include "intel_gt.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
new file mode 100644 (file)
index 0000000..60511f3
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_ENGINE_REGS__
+#define __INTEL_ENGINE_REGS__
+
+#include "i915_reg_defs.h"
+
+#define RING_TAIL(base)                                _MMIO((base) + 0x30)
+#define   TAIL_ADDR                            0x001FFFF8
+#define RING_HEAD(base)                                _MMIO((base) + 0x34)
+#define   HEAD_WRAP_COUNT                      0xFFE00000
+#define   HEAD_WRAP_ONE                                0x00200000
+#define   HEAD_ADDR                            0x001FFFFC
+#define RING_START(base)                       _MMIO((base) + 0x38)
+#define RING_CTL(base)                         _MMIO((base) + 0x3c)
+#define   RING_CTL_SIZE(size)                  ((size) - PAGE_SIZE) /* in bytes -> pages */
+#define   RING_NR_PAGES                                0x001FF000
+#define   RING_REPORT_MASK                     0x00000006
+#define   RING_REPORT_64K                      0x00000002
+#define   RING_REPORT_128K                     0x00000004
+#define   RING_NO_REPORT                       0x00000000
+#define   RING_VALID_MASK                      0x00000001
+#define   RING_VALID                           0x00000001
+#define   RING_INVALID                         0x00000000
+#define   RING_WAIT_I8XX                       (1 << 0) /* gen2, PRBx_HEAD */
+#define   RING_WAIT                            (1 << 11) /* gen3+, PRBx_CTL */
+#define   RING_WAIT_SEMAPHORE                  (1 << 10) /* gen6+ */
+#define RING_SYNC_0(base)                      _MMIO((base) + 0x40)
+#define RING_SYNC_1(base)                      _MMIO((base) + 0x44)
+#define RING_SYNC_2(base)                      _MMIO((base) + 0x48)
+#define GEN6_RVSYNC                            (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC                            (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC                           (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC                            (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC                            (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC                           (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC                            (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC                            (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC                           (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC                           (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC                           (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC                           (RING_SYNC_2(VEBOX_RING_BASE))
+#define RING_PSMI_CTL(base)                    _MMIO((base) + 0x50)
+#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE                REG_BIT(12)
+#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE       REG_BIT(10)
+#define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define   GEN6_BSD_GO_INDICATOR                        REG_BIT(4)
+#define   GEN6_BSD_SLEEP_INDICATOR             REG_BIT(3)
+#define   GEN6_BSD_SLEEP_FLUSH_DISABLE         REG_BIT(2)
+#define   GEN6_PSMI_SLEEP_MSG_DISABLE          REG_BIT(0)
+#define RING_MAX_IDLE(base)                    _MMIO((base) + 0x54)
+#define  PWRCTX_MAXCNT(base)                   _MMIO((base) + 0x54)
+#define    IDLE_TIME_MASK                      0xFFFFF
+#define RING_ACTHD_UDW(base)                   _MMIO((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base)                        _MMIO((base) + 0x60) /* gen8+ */
+#define RING_IPEIR(base)                       _MMIO((base) + 0x64)
+#define RING_IPEHR(base)                       _MMIO((base) + 0x68)
+#define RING_INSTDONE(base)                    _MMIO((base) + 0x6c)
+#define RING_INSTPS(base)                      _MMIO((base) + 0x70)
+#define RING_DMA_FADD(base)                    _MMIO((base) + 0x78)
+#define RING_ACTHD(base)                       _MMIO((base) + 0x74)
+#define RING_HWS_PGA(base)                     _MMIO((base) + 0x80)
+#define RING_CMD_BUF_CCTL(base)                        _MMIO((base) + 0x84)
+#define IPEIR(base)                            _MMIO((base) + 0x88)
+#define IPEHR(base)                            _MMIO((base) + 0x8c)
+#define RING_ID(base)                          _MMIO((base) + 0x8c)
+#define RING_NOPID(base)                       _MMIO((base) + 0x94)
+#define RING_HWSTAM(base)                      _MMIO((base) + 0x98)
+#define RING_MI_MODE(base)                     _MMIO((base) + 0x9c)
+#define RING_IMR(base)                         _MMIO((base) + 0xa8)
+#define RING_EIR(base)                         _MMIO((base) + 0xb0)
+#define RING_EMR(base)                         _MMIO((base) + 0xb4)
+#define RING_ESR(base)                         _MMIO((base) + 0xb8)
+#define RING_INSTPM(base)                      _MMIO((base) + 0xc0)
+#define RING_CMD_CCTL(base)                    _MMIO((base) + 0xc4)
+#define ACTHD(base)                            _MMIO((base) + 0xc8)
+#define RING_RESET_CTL(base)                   _MMIO((base) + 0xd0)
+#define   RESET_CTL_CAT_ERROR                  REG_BIT(2)
+#define   RESET_CTL_READY_TO_RESET             REG_BIT(1)
+#define   RESET_CTL_REQUEST_RESET              REG_BIT(0)
+#define DMA_FADD_I8XX(base)                    _MMIO((base) + 0xd0)
+#define RING_BBSTATE(base)                     _MMIO((base) + 0x110)
+#define   RING_BB_PPGTT                                (1 << 5)
+#define RING_SBBADDR(base)                     _MMIO((base) + 0x114) /* hsw+ */
+#define RING_SBBSTATE(base)                    _MMIO((base) + 0x118) /* hsw+ */
+#define RING_SBBADDR_UDW(base)                 _MMIO((base) + 0x11c) /* gen8+ */
+#define RING_BBADDR(base)                      _MMIO((base) + 0x140)
+#define RING_BBADDR_UDW(base)                  _MMIO((base) + 0x168) /* gen8+ */
+#define CCID(base)                             _MMIO((base) + 0x180)
+#define   CCID_EN                              BIT(0)
+#define   CCID_EXTENDED_STATE_RESTORE          BIT(2)
+#define   CCID_EXTENDED_STATE_SAVE             BIT(3)
+#define RING_BB_PER_CTX_PTR(base)              _MMIO((base) + 0x1c0) /* gen8+ */
+#define RING_INDIRECT_CTX(base)                        _MMIO((base) + 0x1c4) /* gen8+ */
+#define RING_INDIRECT_CTX_OFFSET(base)         _MMIO((base) + 0x1c8) /* gen8+ */
+#define ECOSKPD(base)                          _MMIO((base) + 0x1d0)
+#define   ECO_CONSTANT_BUFFER_SR_DISABLE       REG_BIT(4)
+#define   ECO_GATING_CX_ONLY                   REG_BIT(3)
+#define   GEN6_BLITTER_FBC_NOTIFY              REG_BIT(3)
+#define   ECO_FLIP_DONE                                REG_BIT(0)
+#define   GEN6_BLITTER_LOCK_SHIFT              16
+
+#define BLIT_CCTL(base)                                _MMIO((base) + 0x204)
+#define   BLIT_CCTL_DST_MOCS_MASK              REG_GENMASK(14, 8)
+#define   BLIT_CCTL_SRC_MOCS_MASK              REG_GENMASK(6, 0)
+#define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
+                         BLIT_CCTL_SRC_MOCS_MASK)
+#define   BLIT_CCTL_MOCS(dst, src)                                    \
+               (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
+                REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
+
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
+                           CMD_CCTL_READ_OVERRIDE_MASK)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read)                                  \
+               (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+                REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
+#define RING_PP_DIR_DCLV(base)                 _MMIO((base) + 0x220)
+#define   PP_DIR_DCLV_2G                       0xffffffff
+#define RING_PP_DIR_BASE(base)                 _MMIO((base) + 0x228)
+#define RING_ELSP(base)                                _MMIO((base) + 0x230)
+#define RING_EXECLIST_STATUS_LO(base)          _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base)          _MMIO((base) + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(base)             _MMIO((base) + 0x244)
+#define          CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   REG_BIT(0)
+#define   CTX_CTRL_RS_CTX_ENABLE               REG_BIT(1)
+#define          CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT      REG_BIT(2)
+#define          CTX_CTRL_INHIBIT_SYN_CTX_SWITCH       REG_BIT(3)
+#define          GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE     REG_BIT(8)
+#define RING_SEMA_WAIT_POLL(base)              _MMIO((base) + 0x24c)
+#define GEN8_RING_PDP_UDW(base, n)             _MMIO((base) + 0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(base, n)             _MMIO((base) + 0x270 + (n) * 8)
+#define RING_MODE_GEN7(base)                   _MMIO((base) + 0x29c)
+#define   GFX_RUN_LIST_ENABLE                  (1 << 15)
+#define   GFX_INTERRUPT_STEERING               (1 << 14)
+#define   GFX_TLB_INVALIDATE_EXPLICIT          (1 << 13)
+#define   GFX_SURFACE_FAULT_ENABLE             (1 << 12)
+#define   GFX_REPLAY_MODE                      (1 << 11)
+#define   GFX_PSMI_GRANULARITY                 (1 << 10)
+#define   GFX_PPGTT_ENABLE                     (1 << 9)
+#define   GEN8_GFX_PPGTT_48B                   (1 << 7)
+#define   GFX_FORWARD_VBLANK_MASK              (3 << 5)
+#define   GFX_FORWARD_VBLANK_NEVER             (0 << 5)
+#define   GFX_FORWARD_VBLANK_ALWAYS            (1 << 5)
+#define   GFX_FORWARD_VBLANK_COND              (2 << 5)
+#define   GEN11_GFX_DISABLE_LEGACY_MODE                (1 << 3)
+#define RING_TIMESTAMP(base)                   _MMIO((base) + 0x358)
+#define RING_TIMESTAMP_UDW(base)               _MMIO((base) + 0x358 + 4)
+#define RING_CONTEXT_STATUS_PTR(base)          _MMIO((base) + 0x3a0)
+#define RING_CTX_TIMESTAMP(base)               _MMIO((base) + 0x3a8) /* gen8+ */
+#define RING_FORCE_TO_NONPRIV(base, i)         _MMIO(((base) + 0x4D0) + (i) * 4)
+#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
+#define   RING_FORCE_TO_NONPRIV_ACCESS_RW      (0 << 28)    /* CFL+ & Gen11+ */
+#define   RING_FORCE_TO_NONPRIV_ACCESS_RD      (1 << 28)
+#define   RING_FORCE_TO_NONPRIV_ACCESS_WR      (2 << 28)
+#define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
+#define   RING_FORCE_TO_NONPRIV_ACCESS_MASK    (3 << 28)
+#define   RING_FORCE_TO_NONPRIV_RANGE_1                (0 << 0)     /* CFL+ & Gen11+ */
+#define   RING_FORCE_TO_NONPRIV_RANGE_4                (1 << 0)
+#define   RING_FORCE_TO_NONPRIV_RANGE_16       (2 << 0)
+#define   RING_FORCE_TO_NONPRIV_RANGE_64       (3 << 0)
+#define   RING_FORCE_TO_NONPRIV_RANGE_MASK     (3 << 0)
+#define   RING_FORCE_TO_NONPRIV_MASK_VALID     \
+       (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
+#define   RING_MAX_NONPRIV_SLOTS  12
+
+#define RING_EXECLIST_SQ_CONTENTS(base)                _MMIO((base) + 0x510)
+#define RING_PP_DIR_BASE_READ(base)            _MMIO((base) + 0x518)
+#define RING_EXECLIST_CONTROL(base)            _MMIO((base) + 0x550)
+#define          EL_CTRL_LOAD                          REG_BIT(0)
+
+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
+#define GEN8_RING_CS_GPR(base, n)              _MMIO((base) + 0x600 + (n) * 8)
+#define GEN8_RING_CS_GPR_UDW(base, n)          _MMIO((base) + 0x600 + (n) * 8 + 4)
+
+#define RING_HWS_PGA_GEN6(base)        _MMIO((base) + 0x2080)
+
+#define VDBOX_CGCTL3F10(base)                  _MMIO((base) + 0x3f10)
+#define   IECPUNIT_CLKGATE_DIS                 REG_BIT(22)
+
+#define VDBOX_CGCTL3F18(base)                  _MMIO((base) + 0x3f18)
+#define   ALNUNIT_CLKGATE_DIS                  REG_BIT(13)
+
+
+#endif /* __INTEL_ENGINE_REGS__ */

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index bedb80057046a976f45b0698ac6e386c3394b641..ea8291361d659c9436933caf230c7741d21439e1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -116,6 +116,7 @@
 #include "intel_context.h"
 #include "intel_engine_heartbeat.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_engine_stats.h"
 #include "intel_execlists_submission.h"
 #include "intel_gt.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f2422d48be32d8af3d393fdb1b7fef1240849f93..4814453ab5abf4c50c3e30a4cc47360eac32c108 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -10,6 +10,7 @@
 #include "gem/i915_gem_lmem.h"
 #include "i915_drv.h"
 #include "intel_context.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_buffer_pool.h"
 #include "intel_gt_clock_utils.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 56156cf18c4130fe1ffe7954eb13eecc9f435dbf..1530227c4b918f4dd9def9af13fd60c06226878a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_perf.h"
 #include "intel_engine.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_lrc.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index f785d0ed238f5c0b285eeae9c4890174ccf23994..304000c7e34537be36b325f33ecca7feb40ce672 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -53,21 +53,6 @@
 #define GEN8_EXECLISTS_STATUS_BUF 0x370
 #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
 
-/* Execlists regs */
-#define RING_ELSP(base)                                _MMIO((base) + 0x230)
-#define RING_EXECLIST_STATUS_LO(base)          _MMIO((base) + 0x234)
-#define RING_EXECLIST_STATUS_HI(base)          _MMIO((base) + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(base)             _MMIO((base) + 0x244)
-#define          CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   REG_BIT(0)
-#define   CTX_CTRL_RS_CTX_ENABLE               REG_BIT(1)
-#define          CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT      REG_BIT(2)
-#define          CTX_CTRL_INHIBIT_SYN_CTX_SWITCH       REG_BIT(3)
-#define          GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE     REG_BIT(8)
-#define RING_CONTEXT_STATUS_PTR(base)          _MMIO((base) + 0x3a0)
-#define RING_EXECLIST_SQ_CONTENTS(base)                _MMIO((base) + 0x510)
-#define RING_EXECLIST_CONTROL(base)            _MMIO((base) + 0x550)
-#define          EL_CTRL_LOAD                          REG_BIT(0)
-
 /*
  * The docs specify that the write pointer wraps around after 5h, "After status
  * is written out to the last available status QW at offset 5h, this pointer

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 68ad99ac83e5d3961546ae6112cc6806445d74be..8be1d005d53bfd683ac66d19207f56887479cfc1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
 
 #include "i915_drv.h"
 #include "i915_vgpu.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_pcode.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index c5bfcbe568907d8d9fb3eba46af5ecd0dad0dfe6..5000608189da195a0b3a52deb4f69185b7da9ba6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -16,6 +16,7 @@
 #include "i915_irq.h"
 #include "intel_breadcrumbs.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 2fdd52b620921eb732c39af27dccc0e16c22ccee..723055340c9bc191ee8aa10ebb178e3c0093ea72 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -9,6 +9,7 @@
 #include "i915_drv.h"
 #include "i915_vma.h"
 #include "intel_engine.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_ring.h"
 #include "intel_timeline.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5408bc18a58e20e23f57e1b850d63384b22cf6db..0f1aa1c275b2cbd69a600e279f4d1f83556672ca 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -11,6 +11,7 @@
 #include "i915_mitigations.h"
 #include "intel_breadcrumbs.h"
 #include "intel_context.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_reset.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f5ccc21761c312282f10eca7f9cc3bb11bd356be..a7a0a3acbacbe455b07f7cc2ce74a6ca93869440 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
 #include "i915_drv.h"
 #include "intel_context.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_ring.h"

diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 75569666105d9178f949a7bb71f80e881b7b1acc..0035be4bf58bec04f9f08b434281f6fda66d31a2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -6,6 +6,7 @@
 #include <linux/sort.h>
 
 #include "i915_selftest.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt_clock_utils.h"
 #include "selftest_engine.h"

diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 55c5cdb99f450c299f5efd9ee2cdb79098e82996..3dec126fb910fe0b022633bec04f8f16bb554177 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -5,6 +5,7 @@
 
 #include <linux/sort.h>
 
+#include "intel_engine_regs.h"
 #include "intel_gt_clock_utils.h"
 
 #include "selftest_llc.h"

diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 7ee2513e15f91c4511680e2b1902e2556a8e3a48..bd170ba1cf007989b7a621f905be12d7bc1db795 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -8,6 +8,7 @@
 
 #include "intel_engine_heartbeat.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"

diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index d0b6a3afcf44e0c1028c780b9c4049359b4bced5..72a04a1a16785df07cc93268ab7f68085fdbcb89 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -8,6 +8,7 @@
 #include "intel_context.h"
 #include "intel_engine_heartbeat.h"
 #include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_gt_requests.h"

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 621c893a009f9e9e11eb25043b36798f6d0e7dca..4d5611291e28a5c4be1d618ac3150a33b5d86c44 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -5,6 +5,7 @@
 
 #include <linux/bsearch.h>
 
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_lrc.h"
 #include "gt/shmem_utils.h"

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c48557dfa04c4a73ef2dbdb51134722fe0b40142..4333d139b090efd72360b4277bb3806d4309b271 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -9,8 +9,9 @@
 #include "gt/gen8_engine_cs.h"
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_context.h"
-#include "gt/intel_engine_pm.h"
 #include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c4118b8082682f471a4de82701a0636acaabb865..733e68ea210ac01c15c8f72e63c5b1f661e6dc3e 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -37,6 +37,7 @@
 #include <linux/slab.h>
 
 #include "i915_drv.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_ring.h"

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index abc81cdc9e5d5e626c343d03ad6eb53203a3220c..99d3534d2bd8c26f5aa25124841621286852cf89 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -35,6 +35,7 @@
 
 #include "i915_drv.h"
 #include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_ring.h"
 #include "gvt.h"

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h
index b6b69777af4953fb2db84d54b990517d7881f7d3..128fd7f4d5091078db7f2bb250a252537dc9356f 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
@@ -38,6 +38,7 @@
 
 #include <linux/types.h>
 
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_types.h"
 #include "gt/intel_lrc_reg.h"
 #include "i915_reg.h"

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index a804373bcd177e75cc19466e663cb4f9f004e7d1..96c3980510849bf8b8aa294a9d34ab63c30385b0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -26,6 +26,7 @@
  */
 
 #include "gt/intel_engine.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 
 #include "i915_cmd_parser.h"

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2a2d7643b5511dbd49a205744776333b9101fa06..b3fc8917598a377b588a3b80951927978c2b0610 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -41,6 +41,7 @@
 
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_lmem.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c83fd306ce8ccba00ab472240829b..aa21e9fe3c78832ef87db1b2cf12f593825fffed 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
 
 #include "gem/i915_gem_context.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_execlists_submission.h"
 #include "gt/intel_gpu_commands.h"

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 0b488d49694ca040848235cf84c32aff2c48ed4a..290505b432bc26d6fe5a4ce71accdd18442b8e86 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
 
 #include "gt/intel_engine.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_rc6.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca815da75380f7ed4cf3679f8372b9db39bfeaaa..1a7ffdeb8df12e9a9424ac0e8b7aaa6507def20f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -272,14 +272,6 @@
 #define GEN12_SFC_DONE(n)              _MMIO(0x1cc000 + (n) * 0x1000)
 #define GEN12_SFC_DONE_MAX             4
 
-#define RING_PP_DIR_BASE(base)         _MMIO((base) + 0x228)
-#define RING_PP_DIR_BASE_READ(base)    _MMIO((base) + 0x518)
-#define RING_PP_DIR_DCLV(base)         _MMIO((base) + 0x220)
-#define   PP_DIR_DCLV_2G               0xffffffff
-
-#define GEN8_RING_PDP_UDW(base, n)     _MMIO((base) + 0x270 + (n) * 8 + 4)
-#define GEN8_RING_PDP_LDW(base, n)     _MMIO((base) + 0x270 + (n) * 8)
-
 #define GEN8_R_PWR_CLK_STATE           _MMIO(0x20C8)
 #define   GEN8_RPCS_ENABLE             (1 << 31)
 #define   GEN8_RPCS_S_CNT_ENABLE       (1 << 18)
@@ -2188,71 +2180,8 @@
 #define XEHP_VEBOX3_RING_BASE          0x1e8000
 #define XEHP_VEBOX4_RING_BASE          0x1f8000
 #define BLT_RING_BASE          0x22000
-#define RING_TAIL(base)                _MMIO((base) + 0x30)
-#define RING_HEAD(base)                _MMIO((base) + 0x34)
-#define RING_START(base)       _MMIO((base) + 0x38)
-#define RING_CTL(base)         _MMIO((base) + 0x3c)
-#define   RING_CTL_SIZE(size)  ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_SYNC_0(base)      _MMIO((base) + 0x40)
-#define RING_SYNC_1(base)      _MMIO((base) + 0x44)
-#define RING_SYNC_2(base)      _MMIO((base) + 0x48)
-#define GEN6_RVSYNC    (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC    (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_RVESYNC   (RING_SYNC_2(RENDER_RING_BASE))
-#define GEN6_VBSYNC    (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_VRSYNC    (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VVESYNC   (RING_SYNC_2(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC    (RING_SYNC_0(BLT_RING_BASE))
-#define GEN6_BVSYNC    (RING_SYNC_1(BLT_RING_BASE))
-#define GEN6_BVESYNC   (RING_SYNC_2(BLT_RING_BASE))
-#define GEN6_VEBSYNC   (RING_SYNC_0(VEBOX_RING_BASE))
-#define GEN6_VERSYNC   (RING_SYNC_1(VEBOX_RING_BASE))
-#define GEN6_VEVSYNC   (RING_SYNC_2(VEBOX_RING_BASE))
-#define GEN6_NOSYNC    INVALID_MMIO_REG
-#define RING_PSMI_CTL(base)    _MMIO((base) + 0x50)
-#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE                REG_BIT(12)
-#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE       REG_BIT(10)
-#define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define   GEN6_BSD_GO_INDICATOR                        REG_BIT(4)
-#define   GEN6_BSD_SLEEP_INDICATOR             REG_BIT(3)
-#define   GEN6_BSD_SLEEP_FLUSH_DISABLE         REG_BIT(2)
-#define   GEN6_PSMI_SLEEP_MSG_DISABLE          REG_BIT(0)
-#define RING_MAX_IDLE(base)    _MMIO((base) + 0x54)
-#define RING_HWS_PGA(base)     _MMIO((base) + 0x80)
-#define RING_ID(base)          _MMIO((base) + 0x8c)
-#define RING_HWS_PGA_GEN6(base)        _MMIO((base) + 0x2080)
-
-#define RING_CMD_CCTL(base)    _MMIO((base) + 0xc4)
-/*
- * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
- * The lsb of each can be considered a separate enabling bit for encryption.
- * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
- * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
- * 15:14 == Reserved => 31:30 are set to 0.
- */
-#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
-#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
-#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
-                           CMD_CCTL_READ_OVERRIDE_MASK)
-#define CMD_CCTL_MOCS_OVERRIDE(write, read)                                  \
-               (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
-                REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
-
-#define BLIT_CCTL(base) _MMIO((base) + 0x204)
-#define   BLIT_CCTL_DST_MOCS_MASK       REG_GENMASK(14, 8)
-#define   BLIT_CCTL_SRC_MOCS_MASK       REG_GENMASK(6, 0)
-#define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
-                         BLIT_CCTL_SRC_MOCS_MASK)
-#define   BLIT_CCTL_MOCS(dst, src)                                    \
-               (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
-                REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
-
-#define RING_RESET_CTL(base)   _MMIO((base) + 0xd0)
-#define   RESET_CTL_CAT_ERROR     REG_BIT(2)
-#define   RESET_CTL_READY_TO_RESET REG_BIT(1)
-#define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
-
-#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+
+
 
 #define HSW_GTT_CACHE_EN       _MMIO(0x4024)
 #define   GTT_CACHE_EN_ALL     0xF0007FFF
@@ -2307,49 +2236,6 @@
 #define   AUX_INV              REG_BIT(0)
 #define BLT_HWS_PGA_GEN7       _MMIO(0x04280)
 #define VEBOX_HWS_PGA_GEN7     _MMIO(0x04380)
-#define RING_ACTHD(base)       _MMIO((base) + 0x74)
-#define RING_ACTHD_UDW(base)   _MMIO((base) + 0x5c)
-#define RING_NOPID(base)       _MMIO((base) + 0x94)
-#define RING_IMR(base)         _MMIO((base) + 0xa8)
-#define RING_HWSTAM(base)      _MMIO((base) + 0x98)
-#define RING_TIMESTAMP(base)           _MMIO((base) + 0x358)
-#define RING_TIMESTAMP_UDW(base)       _MMIO((base) + 0x358 + 4)
-#define   TAIL_ADDR            0x001FFFF8
-#define   HEAD_WRAP_COUNT      0xFFE00000
-#define   HEAD_WRAP_ONE                0x00200000
-#define   HEAD_ADDR            0x001FFFFC
-#define   RING_NR_PAGES                0x001FF000
-#define   RING_REPORT_MASK     0x00000006
-#define   RING_REPORT_64K      0x00000002
-#define   RING_REPORT_128K     0x00000004
-#define   RING_NO_REPORT       0x00000000
-#define   RING_VALID_MASK      0x00000001
-#define   RING_VALID           0x00000001
-#define   RING_INVALID         0x00000000
-#define   RING_WAIT_I8XX       (1 << 0) /* gen2, PRBx_HEAD */
-#define   RING_WAIT            (1 << 11) /* gen3+, PRBx_CTL */
-#define   RING_WAIT_SEMAPHORE  (1 << 10) /* gen6+ */
-
-/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
-#define GEN8_RING_CS_GPR(base, n)      _MMIO((base) + 0x600 + (n) * 8)
-#define GEN8_RING_CS_GPR_UDW(base, n)  _MMIO((base) + 0x600 + (n) * 8 + 4)
-
-#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
-#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
-#define   RING_FORCE_TO_NONPRIV_ACCESS_RW      (0 << 28)    /* CFL+ & Gen11+ */
-#define   RING_FORCE_TO_NONPRIV_ACCESS_RD      (1 << 28)
-#define   RING_FORCE_TO_NONPRIV_ACCESS_WR      (2 << 28)
-#define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
-#define   RING_FORCE_TO_NONPRIV_ACCESS_MASK    (3 << 28)
-#define   RING_FORCE_TO_NONPRIV_RANGE_1                (0 << 0)     /* CFL+ & Gen11+ */
-#define   RING_FORCE_TO_NONPRIV_RANGE_4                (1 << 0)
-#define   RING_FORCE_TO_NONPRIV_RANGE_16       (2 << 0)
-#define   RING_FORCE_TO_NONPRIV_RANGE_64       (3 << 0)
-#define   RING_FORCE_TO_NONPRIV_RANGE_MASK     (3 << 0)
-#define   RING_FORCE_TO_NONPRIV_MASK_VALID     \
-                                       (RING_FORCE_TO_NONPRIV_RANGE_MASK \
-                                       | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
-#define   RING_MAX_NONPRIV_SLOTS  12
 
 #define GEN7_TLB_RD_ADDR       _MMIO(0x4700)
 
@@ -2394,23 +2280,11 @@
 #define   GEN11_MCR_SLICE_MASK         GEN11_MCR_SLICE(0xf)
 #define   GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
 #define   GEN11_MCR_SUBSLICE_MASK      GEN11_MCR_SUBSLICE(0x7)
-#define RING_IPEIR(base)       _MMIO((base) + 0x64)
-#define RING_IPEHR(base)       _MMIO((base) + 0x68)
-#define RING_EIR(base)         _MMIO((base) + 0xb0)
-#define RING_EMR(base)         _MMIO((base) + 0xb4)
-#define RING_ESR(base)         _MMIO((base) + 0xb8)
 /*
  * On GEN4, only the render ring INSTDONE exists and has a different
  * layout than the GEN7+ version.
  * The GEN2 counterpart of this register is GEN2_INSTDONE.
  */
-#define RING_INSTDONE(base)    _MMIO((base) + 0x6c)
-#define RING_INSTPS(base)      _MMIO((base) + 0x70)
-#define RING_DMA_FADD(base)    _MMIO((base) + 0x78)
-#define RING_DMA_FADD_UDW(base)        _MMIO((base) + 0x60) /* gen8+ */
-#define RING_INSTPM(base)      _MMIO((base) + 0xc0)
-#define RING_MI_MODE(base)     _MMIO((base) + 0x9c)
-#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
 #define INSTPS         _MMIO(0x2070) /* 965+ only */
 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
 #define ACTHD_I965     _MMIO(0x2074)
@@ -2419,26 +2293,9 @@
 #define HWS_START_ADDRESS_SHIFT        4
 #define PWRCTXA                _MMIO(0x2088) /* 965GM+ only */
 #define   PWRCTX_EN    (1 << 0)
-#define IPEIR(base)    _MMIO((base) + 0x88)
-#define IPEHR(base)    _MMIO((base) + 0x8c)
 #define GEN2_INSTDONE  _MMIO(0x2090)
 #define NOPID          _MMIO(0x2094)
 #define HWSTAM         _MMIO(0x2098)
-#define DMA_FADD_I8XX(base)    _MMIO((base) + 0xd0)
-#define RING_BBSTATE(base)     _MMIO((base) + 0x110)
-#define   RING_BB_PPGTT                (1 << 5)
-#define RING_SBBADDR(base)     _MMIO((base) + 0x114) /* hsw+ */
-#define RING_SBBSTATE(base)    _MMIO((base) + 0x118) /* hsw+ */
-#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
-#define RING_BBADDR(base)      _MMIO((base) + 0x140)
-#define RING_BBADDR_UDW(base)  _MMIO((base) + 0x168) /* gen8+ */
-#define RING_BB_PER_CTX_PTR(base)      _MMIO((base) + 0x1c0) /* gen8+ */
-#define RING_INDIRECT_CTX(base)                _MMIO((base) + 0x1c4) /* gen8+ */
-#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
-#define RING_CTX_TIMESTAMP(base)       _MMIO((base) + 0x3a8) /* gen8+ */
-
-#define VDBOX_CGCTL3F10(base)          _MMIO((base) + 0x3f10)
-#define   IECPUNIT_CLKGATE_DIS         REG_BIT(22)
 
 #define ERROR_GEN6     _MMIO(0x40a0)
 #define GEN7_ERR_INT   _MMIO(0x44040)
@@ -2551,22 +2408,6 @@
         GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
 
 #define GFX_MODE       _MMIO(0x2520)
-#define RING_MODE_GEN7(base)   _MMIO((base) + 0x29c)
-#define   GFX_RUN_LIST_ENABLE          (1 << 15)
-#define   GFX_INTERRUPT_STEERING       (1 << 14)
-#define   GFX_TLB_INVALIDATE_EXPLICIT  (1 << 13)
-#define   GFX_SURFACE_FAULT_ENABLE     (1 << 12)
-#define   GFX_REPLAY_MODE              (1 << 11)
-#define   GFX_PSMI_GRANULARITY         (1 << 10)
-#define   GFX_PPGTT_ENABLE             (1 << 9)
-#define   GEN8_GFX_PPGTT_48B           (1 << 7)
-
-#define   GFX_FORWARD_VBLANK_MASK      (3 << 5)
-#define   GFX_FORWARD_VBLANK_NEVER     (0 << 5)
-#define   GFX_FORWARD_VBLANK_ALWAYS    (1 << 5)
-#define   GFX_FORWARD_VBLANK_COND      (2 << 5)
-
-#define   GEN11_GFX_DISABLE_LEGACY_MODE        (1 << 3)
 
 #define VLV_GU_CTL0    _MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1    _MMIO(VLV_DISPLAY_BASE + 0x2034)
@@ -2607,7 +2448,6 @@
 #define   INSTPM_FORCE_ORDERING                                (1 << 7) /* GEN6+ */
 #define   INSTPM_TLB_INVALIDATE        (1 << 9)
 #define   INSTPM_SYNC_FLUSH    (1 << 5)
-#define ACTHD(base)    _MMIO((base) + 0xc8)
 #define MEM_MODE       _MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -2746,12 +2586,6 @@
 #define GFX_FLSH_CNTL  _MMIO(0x2170) /* 915+ only */
 #define GFX_FLSH_CNTL_GEN6     _MMIO(0x101008)
 #define   GFX_FLSH_CNTL_EN     (1 << 0)
-#define ECOSKPD(base)          _MMIO((base) + 0x1d0)
-#define   ECO_CONSTANT_BUFFER_SR_DISABLE       REG_BIT(4)
-#define   ECO_GATING_CX_ONLY                   REG_BIT(3)
-#define   GEN6_BLITTER_FBC_NOTIFY              REG_BIT(3)
-#define   ECO_FLIP_DONE                                REG_BIT(0)
-#define   GEN6_BLITTER_LOCK_SHIFT              16
 
 #define CACHE_MODE_0_GEN7      _MMIO(0x7000) /* IVB+ */
 #define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -3813,10 +3647,6 @@
 /*
  * Logical Context regs
  */
-#define CCID(base)                     _MMIO((base) + 0x180)
-#define   CCID_EN                      BIT(0)
-#define   CCID_EXTENDED_STATE_RESTORE  BIT(2)
-#define   CCID_EXTENDED_STATE_SAVE     BIT(3)
 /*
  * Notes on SNB/IVB/VLV context size:
  * - Power context is saved elsewhere (LLC or stolen)
@@ -8860,8 +8690,6 @@ enum {
 #define           RC6_CTX_IN_DRAM                      (1 << 0)
 #define  RC6_CTX_BASE                          _MMIO(0xD48)
 #define    RC6_CTX_BASE_MASK                   0xFFFFFFF0
-#define  PWRCTX_MAXCNT(base)                   _MMIO((base) + 0x54)
-#define    IDLE_TIME_MASK                      0xFFFFF
 #define  FORCEWAKE                             _MMIO(0xA18C)
 #define  FORCEWAKE_VLV                         _MMIO(0x1300b0)
 #define  FORCEWAKE_ACK_VLV                     _MMIO(0x1300b4)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 42cd173577714ae41884850a7638f72f6ef5ce9d..55934129a6be4646c3c9958e5b803b9a393f99c0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -35,6 +35,7 @@
 #include "gt/intel_context.h"
 #include "gt/intel_engine.h"
 #include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_reset.h"
 #include "gt/intel_ring.h"

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fd622f959a2a40a8f2e1bb322273fa93db71ae60..76e1da70f4ad0592cbc58072e8afe6076df8871e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
 #include "display/intel_sprite.h"
 #include "display/skl_universal_plane.h"
 
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_llc.h"
 
 #include "i915_drv.h"

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 722910d02b5fff8c7131732d239812005af84e2e..fefaf63dfb88d684d202e4fecb742cdbde201e7a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -23,7 +23,7 @@
 
 #include <linux/pm_runtime.h>
 
-#include "gt/intel_lrc_reg.h" /* for shadow reg list */
+#include "gt/intel_engine_regs.h"
 
 #include "i915_drv.h"
 #include "i915_iosf_mbi.h"