We support up to 6 levels, but those are encoded as 10b according to the
AMD IOMMU spec (chapter 3.3.1, Extended Feature Register).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
#define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000
/* AMDVI paging mode */
-#define AMDVI_GATS_MODE (6ULL << 12)
-#define AMDVI_HATS_MODE (6ULL << 10)
+#define AMDVI_GATS_MODE (2ULL << 12)
+#define AMDVI_HATS_MODE (2ULL << 10)
/* IOTLB */
#define AMDVI_IOTLB_MAX_SIZE 1024