arm64: dts: renesas: r9a07g043: Add SDHI nodes

Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index f24756d89bc2135ab58f8e41096b824fcc308f8e..c013d4fbe9f79c5a147e209419caa260b95880c6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -334,13 +334,35 @@
                };
 
                sdhi0: mmc@11c00000  {
+                       compatible = "renesas,sdhi-r9a07g043",
+                                    "renesas,rcar-gen3-sdhi";
                        reg = <0x0 0x11c00000 0 0x10000>;
-                       /* place holder */
+                       interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
+                                <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
+                                <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A07G043_SDHI0_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
                };
 
                sdhi1: mmc@11c10000 {
+                       compatible = "renesas,sdhi-r9a07g043",
+                                    "renesas,rcar-gen3-sdhi";
                        reg = <0x0 0x11c10000 0 0x10000>;
-                       /* place holder */
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
+                                <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
+                                <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A07G043_SDHI1_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
                };
 
                phyrst: usbphy-ctrl@11c40000 {