drm/msm/dp: enable SDP and SDE periph flush update

DP controller can be setup to operate in either SDP update flush mode or
peripheral flush mode based on the DP controller hardware version.

Starting in DP v1.2, the hardware documents require the use of
peripheral flush mode for SDP packets such as PPS OR VSC SDP packets.

In-line with this guidance, lets program the DP controller to use
peripheral flush mode starting DP v1.2

Changes in v4:
	- Clear up that DP_MAINLINK_CTRL_FLUSH_MODE register requires
	  the use of bits [24:23]
	- Modify macros DP_MAINLINK_FLUSH_MODE_UPDATE_SDP and
	  DP_MAINLINK_FLUSH_MODE_SDP_PERIPH_UPDATE to explicitly set
	  their values in the bits of DP_MAINLINK_CTRL_FLUSH_MODE_MASK

Changes in v3:
	- Clear up that the DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE
	  macro is setting bits [24:23] to a value of 3

Changes in v2:
	- Use the original dp_catalog_hw_revision() function to
	  correctly check the DP HW version

Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579621/
Link: https://lore.kernel.org/r/20240222194025.25329-16-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 0bdab9bd21b9131a53f68b187eb8f720ce0b4902..3e7c84cdef472c0c71cfb7f06cd565d6d65aa3bd 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -450,6 +450,23 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
        dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
 }
 
+void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
+{
+       u32 mainlink_ctrl, hw_revision;
+       struct dp_catalog_private *catalog = container_of(dp_catalog,
+                               struct dp_catalog_private, dp_catalog);
+
+       mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+
+       hw_revision = dp_catalog_hw_revision(dp_catalog);
+       if (hw_revision >= DP_HW_VERSION_1_2)
+               mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE;
+       else
+               mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP;
+
+       dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+}
+
 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
                                        u32 rate, u32 stream_rate_khz,
                                        bool fixed_nvid, bool is_ycbcr_420)

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index a9c70054d4a41c398b993f935b41168e80b0bcb3..75ec290127c775cc009e3809d6b8314e57f60115 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -96,6 +96,7 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
 void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
 void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
 void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog);
 void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
                                u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420);

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 24787aa738ccd9d48d3860e49344a93fb28b85db..c4dda1faef677071acd254dcb8942924c1d94060 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -179,6 +179,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
 
        dp_catalog_ctrl_lane_mapping(ctrl->catalog);
        dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
+       dp_catalog_setup_peripheral_flush(ctrl->catalog);
 
        dp_ctrl_config_ctrl(ctrl);
 

diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index aa9f6c3e4ddeb716f93c5ab37bb6cf8bdd746506..3835c7f5cb984406f8fc52ea765ef2315e0d175b 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -6,6 +6,9 @@
 #ifndef _DP_REG_H_
 #define _DP_REG_H_
 
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
 /* DP_TX Registers */
 #define REG_DP_HW_VERSION                      (0x00000000)
 
@@ -102,6 +105,9 @@
 #define DP_MAINLINK_CTRL_ENABLE                        (0x00000001)
 #define DP_MAINLINK_CTRL_RESET                 (0x00000002)
 #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER   (0x00000010)
+#define DP_MAINLINK_CTRL_FLUSH_MODE_MASK       GENMASK(24, 23)
+#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP      FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1)
+#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE       FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3)
 #define DP_MAINLINK_FB_BOUNDARY_SEL            (0x02000000)
 
 #define REG_DP_STATE_CTRL                      (0x00000004)