cpu: Define ArchCPU

For all targets, do this just before including exec/cpu-all.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 9ec92bf09dd3469c8709637b6256652311006655..5af0b6c542a807b5c5c84f604210d7508cec7226 100644 (file)
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -305,6 +305,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 #define cpu_signal_handler cpu_alpha_signal_handler
 
 typedef CPUAlphaState CPUArchState;
+typedef AlphaCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ccf581a84c1661e63c5ae3d502b4eec6362b377b..4ebb6349f1738fb31bcb5de12f607af36c14ede4 100644 (file)
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3126,6 +3126,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
 }
 
 typedef CPUARMState CPUArchState;
+typedef ARMCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 2ee5417ead1cd8c01c807974837d6b6bbed56a09..e978eb953985fbca339cd418a46bdaaae488edaf 100644 (file)
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -285,6 +285,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 
 typedef CPUCRISState CPUArchState;
+typedef CRISCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7fd755a753abcf8b963f9b32ce0412a3579dfb73..6eef107370bb8783aef8ff4403bf5f4c448cadff 100644 (file)
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -231,6 +231,7 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
 #define ENV_OFFSET      offsetof(HPPACPU, env)
 
 typedef CPUHPPAState CPUArchState;
+typedef HPPACPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 81931fc51066519e61aa55a64f9db547fa1148b2..65f8f4d16c8455d44bf22bd61e8afafce02aa040 100644 (file)
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1753,6 +1753,7 @@ static inline target_long lshift(target_long x, int n)
 void tcg_x86_init(void);
 
 typedef CPUX86State CPUArchState;
+typedef X86CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 #include "svm.h"

diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 86f6c7b0af5959f3d64802b829e137077fb2cd85..08c360bd16129c5c2388e3e538264ac7aedd0cf4 100644 (file)
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -257,6 +257,7 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        bool probe, uintptr_t retaddr);
 
 typedef CPULM32State CPUArchState;
+typedef LM32CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 4465a66145d67de727de919617d9a77fbee11a19..1d30b73bdfa0388bc36984593f3909dce32db7bd 100644 (file)
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -537,6 +537,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                  MemTxResult response, uintptr_t retaddr);
 
 typedef CPUM68KState CPUArchState;
+typedef M68kCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6170fd452fb619040b251bbd091091179843bbb7..5a7fe3cbf8a4dbaf0c951b62a9e75a9592a4cbf4 100644 (file)
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -366,6 +366,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                      bool probe, uintptr_t retaddr);
 
 typedef CPUMBState CPUArchState;
+typedef MicroBlazeCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6f65822bb1081882adea0ed45e85660c6fdc727d..12527ca104b37dcb9c783eb1c371ab1b95c78a07 100644 (file)
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1113,6 +1113,7 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
 }
 
 typedef CPUMIPSState CPUArchState;
+typedef MIPSCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 1de05158484ed201e911ef08188a48da4fc47ac0..b27b0eabae21b36498ccd63a2a1ede084399bc39 100644 (file)
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -118,6 +118,7 @@ static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch)
 }
 
 typedef CPUMoxieState CPUArchState;
+typedef MoxieCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index cc8e0ab7719a960c911e35dd27ba79c4aa7513b1..5e51f1ae3f0fe88c260cec688780b9cc2391c29c 100644 (file)
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -247,6 +247,7 @@ static inline int cpu_interrupts_enabled(CPUNios2State *env)
 }
 
 typedef CPUNios2State CPUArchState;
+typedef Nios2CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 98361cb04178cd557eb05af8db0fb63ab11c1237..496895693e6129196f38c47f5e115433b9a92eea 100644 (file)
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -364,6 +364,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
 
 typedef CPUOpenRISCState CPUArchState;
+typedef OpenRISCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6478fe7c91aac7f8b30bc74d450c9915b99e465c..17e7213be9feca81c084d89588c6d5af232de50e 100644 (file)
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1376,6 +1376,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
 #endif /* defined(TARGET_PPC64) */
 
 typedef CPUPPCState CPUArchState;
+typedef PowerPCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 509aae0613b1f7c6f358b277fb2813dac22ebd23..8ee5051119921a3670f2cb47a4f77194b8a1ef74 100644 (file)
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -335,6 +335,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
 typedef CPURISCVState CPUArchState;
+typedef RISCVCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 6614c05f309c28b130930acce52f29c866215828..a8c3d702d391f344736520a4b723f3f4bfe5e323 100644 (file)
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -795,6 +795,7 @@ void s390_init_sigp(void);
 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 
 typedef CPUS390XState CPUArchState;
+typedef S390CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index d7a8723d39e19a63713b95787e3ad9d2c697c549..1bdc997290a34f7304e2c4dbbe46a06beff86457 100644 (file)
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -281,6 +281,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
 }
 
 typedef CPUSH4State CPUArchState;
+typedef SuperHCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index fc392c6e87de9715d09aec26dde07437bfbe7fed..ba5904e05af30b948b9e87a9752d4dd184103803 100644 (file)
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -730,6 +730,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 }
 
 typedef CPUSPARCState CPUArchState;
+typedef SPARCCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 2fbf14d508825bf9f5be3e2fc49af515977a450e..042a7a0c711af3c57e57cfd6636561ecfef47d2f 100644 (file)
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -151,6 +151,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
 #define MMU_USER_IDX    0  /* Current memory operation is in user mode */
 
 typedef CPUTLGState CPUArchState;
+typedef TileGXCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 5d3072f2db85f38c8d49a2abbc08ebba92ce2120..8d660df34a2809b8752001f8d09b1ea265210ce4 100644 (file)
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -379,6 +379,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
 }
 
 typedef CPUTriCoreState CPUArchState;
+typedef TriCoreCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 48562949b1d8b19c5f9900a5835b207288a5de61..5c9c4d98c0a3ddc2460b91614838d799fa6e328f 100644 (file)
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -152,6 +152,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
 }
 
 typedef CPUUniCore32State CPUArchState;
+typedef UniCore32CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index e164e18f1889e047ea3bd2653913fabc09a74e67..6e6fb1d8931cabfe34f28fd10c1a35ea962ab29a 100644 (file)
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -800,6 +800,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 }
 
 typedef CPUXtensaState CPUArchState;
+typedef XtensaCPU ArchCPU;
 
 #include "exec/cpu-all.h"