arm64: dts: imx8mp: Add cpu-freq support

Add A53 OPP table and cpu regulator to support cpu-freq driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 68e6c9099f65e37abf43000fe939fdf301284d6a..e910dc22bf43172d68fae1de3450b7e0ed66a0d8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -61,6 +61,7 @@
                        next-level-cache = <&A53_L2>;
                        nvmem-cells = <&cpu_speed_grade>;
                        nvmem-cell-names = "speed_grade";
+                       operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
                };
 
@@ -78,6 +79,7 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
                };
 
@@ -95,6 +97,7 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
                };
 
@@ -112,6 +115,7 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
+                       operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
                };
 
@@ -124,6 +128,35 @@
                };
        };
 
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x8a0>, <0x7>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+
+               opp-1600000000 {
+                       opp-hz = /bits/ 64 <1600000000>;
+                       opp-microvolt = <950000>;
+                       opp-supported-hw = <0xa0>, <0x7>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <1000000>;
+                       opp-supported-hw = <0x20>, <0x3>;
+                       clock-latency-ns = <150000>;
+                       opp-suspend;
+               };
+       };
+
        osc_32k: clock-osc-32k {
                compatible = "fixed-clock";
                #clock-cells = <0>;