phy: qcom-qmp: qserdes-com: Add some more v6 register offsets

Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8faf16a7aa5e47b60eadd4a8d2abc09c673..ec7291424dd1f1bb7f706bbb5b77419f76d0bfda 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -22,6 +22,8 @@
 #define QSERDES_V6_COM_DIV_FRAC_START2_MODE1                   0x34
 #define QSERDES_V6_COM_DIV_FRAC_START3_MODE1                   0x38
 #define QSERDES_V6_COM_HSCLK_SEL_1                             0x3c
+#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1                   0x40
+#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1                   0x44
 #define QSERDES_V6_COM_VCO_TUNE1_MODE1                         0x48
 #define QSERDES_V6_COM_VCO_TUNE2_MODE1                         0x4c
 #define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1              0x50
@@ -48,6 +50,7 @@
 #define QSERDES_V6_COM_VCO_TUNE2_MODE0                         0xac
 #define QSERDES_V6_COM_BG_TIMER                                        0xbc
 #define QSERDES_V6_COM_SSC_EN_CENTER                           0xc0
+#define QSERDES_V6_COM_SSC_ADJ_PER1                            0xc4
 #define QSERDES_V6_COM_SSC_PER1                                        0xcc
 #define QSERDES_V6_COM_SSC_PER2                                        0xd0
 #define QSERDES_V6_COM_PLL_POST_DIV_MUX                                0xd8
@@ -56,6 +59,7 @@
 #define QSERDES_V6_COM_SYS_CLK_CTRL                            0xe4
 #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE                       0xe8
 #define QSERDES_V6_COM_PLL_IVCO                                        0xf4
+#define QSERDES_V6_COM_PLL_IVCO_MODE1                          0xf8
 #define QSERDES_V6_COM_SYSCLK_EN_SEL                           0x110
 #define QSERDES_V6_COM_RESETSM_CNTRL                           0x118
 #define QSERDES_V6_COM_LOCK_CMP_EN                             0x120
@@ -63,6 +67,7 @@
 #define QSERDES_V6_COM_VCO_TUNE_CTRL                           0x13c
 #define QSERDES_V6_COM_VCO_TUNE_MAP                            0x140
 #define QSERDES_V6_COM_VCO_TUNE_INITVAL2                       0x148
+#define QSERDES_V6_COM_VCO_TUNE_MAXVAL2                                0x158
 #define QSERDES_V6_COM_CLK_SELECT                              0x164
 #define QSERDES_V6_COM_CORE_CLK_EN                             0x170
 #define QSERDES_V6_COM_CMN_CONFIG_1                            0x174

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
index 8883e1de730eff83a8ca3cd7065e78fe93e4add8..23ffcfae9efab4a9e081414f9b3bbd0079d34f18 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
@@ -23,6 +23,7 @@
 #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN               0x60
 #define QSERDES_V6_TX_BIST_PATTERN7                            0x7c
 #define QSERDES_V6_TX_LANE_MODE_1                              0x84
+#define QSERDES_V6_TX_LANE_MODE_2                              0x88
 #define QSERDES_V6_TX_LANE_MODE_3                              0x8c
 #define QSERDES_V6_TX_LANE_MODE_4                              0x90
 #define QSERDES_V6_TX_LANE_MODE_5                              0x94