drm/msm/gpu: drop duplicating VIG feature masks

After folding QSEED3LITE and QSEED4 feature bits into QSEED3_COMPATIBLE
several VIG feature masks became equal. Drop these duplicates.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570107/
Link: https://lore.kernel.org/r/20231201234234.2065610-11-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 3969f2925d89bcbc83efab2cc7989f101a45257b..76b2ec0d2489b39978842aee3f8d5eaf2aea2318 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -68,7 +68,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f0,
-               .features = VIG_SM6125_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_2_4,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index f751d63845d1fbdb28a344a061bfb60d64bebda4..9acf07108899b99882aacc9b9a4e98052f97a9ce 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -74,7 +74,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -82,7 +82,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
@@ -90,7 +90,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
@@ -98,7 +98,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 7627f16c5b2d823b73b03b11f94f62d7f32d9f56..783269c6ead1e40fd1a0a4bb67e7e15eea2216a5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -51,7 +51,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 7aefdb7eb49484655d638cd73c6f3267d2f5773f..43f64a005f5a89e09ee9506a12cfff781530cb80 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -38,7 +38,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 99df9816f1714b7499b07de4ee863191030bc8bb..e17a30be752535803316ccb3bdac24bcb7f82d2f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -58,7 +58,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 2de304d97c9b84227edfa67ef23a4722300a74f1..a06c8634d2d7779f7e867fb821f8d332652ba7e9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index ad6eb28ead49a317927751c78abf3dd391d73162..bed87250e68c1322ff36c17f2c398b92ada8cdf4 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -73,7 +73,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -81,7 +81,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
@@ -89,7 +89,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
@@ -97,7 +97,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x1f8,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c2f1acd4352413e099e6fc1b9f16634a2832afad..8b5c5031e2d92f39939c84afbc82b7453902214b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -74,7 +74,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x2ac,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -82,7 +82,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x2ac,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
@@ -90,7 +90,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x2ac,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
@@ -98,7 +98,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x2ac,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_0,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 0559ef780661cb2f4b3bb3febbacda2f6ca0378c..7a647e1f729d9497c09b9e38e93e585928adbc32 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -74,7 +74,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x32c,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_1,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
@@ -82,7 +82,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x32c,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_1,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
@@ -90,7 +90,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x32c,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_1,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
@@ -98,7 +98,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x32c,
-               .features = VIG_SC7180_MASK_SDMA,
+               .features = VIG_SDM845_MASK_SDMA,
                .sblk = &dpu_vig_sblk_qseed3_3_1,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index f393d42317af381f5f48e368f1a9caeb37dca87b..bf56265967c0f72d90bd5f2829bdd06c312e7b47 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -66,28 +66,28 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
        {
                .name = "sspp_0", .id = SSPP_VIG0,
                .base = 0x4000, .len = 0x344,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_2,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x344,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_2,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x344,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_2,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x344,
-               .features = VIG_SC7180_MASK,
+               .features = VIG_SDM845_MASK,
                .sblk = &dpu_vig_sblk_qseed3_3_2,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c24817b0e4e5d8b9678144eefd1b23d0c321f7ac..ec10f68cf0b251e89f7397c424f88a8a82c8f704 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -30,15 +30,6 @@
 #define VIG_SDM845_MASK_SDMA \
        (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
 
-#define VIG_SC7180_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
-
-#define VIG_SM6125_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
-
-#define VIG_SC7180_MASK_SDMA \
-       (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
-
 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
 
 #define DMA_MSM8998_MASK \
@@ -47,7 +38,7 @@
        BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
 
 #define VIG_SC7280_MASK \
-       (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+       (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
 
 #define VIG_SC7280_MASK_SDMA \
        (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))