net/mlx5e: IPsec, Remove unnecessary config flag usage

MLX5_IPSEC_DEV() is always defined, no need to protect it under config
flag CONFIG_MLX5_EN_IPSEC, especially in slow path.

Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Raed Salem <raeds@nvidia.com>
Reviewed-by: Huy Nguyen <huyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index ee86b2b57f4dd1b56a9bb6fc797187940c046cee..f33c38629886a5248a2b80751690629553dcaa4f 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -2068,10 +2068,8 @@ static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
        u32 buf_size = 0;
        int i;
 
-#ifdef CONFIG_MLX5_EN_IPSEC
        if (MLX5_IPSEC_DEV(mdev))
                byte_count += MLX5E_METADATA_ETHER_LEN;
-#endif
 
        if (mlx5e_rx_is_linear_skb(params, xsk)) {
                int frag_stride;

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index 7f5851c612181e42489dddbaa2e6450950ce64f9..cb8e3d2b475045a08f849fb51c4f0c3c1e626ffa 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -1786,12 +1786,10 @@ int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool
                rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 
                rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe;
-#ifdef CONFIG_MLX5_EN_IPSEC
                if (MLX5_IPSEC_DEV(mdev)) {
                        netdev_err(netdev, "MPWQE RQ with IPSec offload not supported\n");
                        return -EINVAL;
                }
-#endif
                if (!rq->handle_rx_cqe) {
                        netdev_err(netdev, "RX handler of MPWQE RQ is not set\n");
                        return -EINVAL;