target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c367604efc642fc8ab2a082373f5b0c98..4b730cd492ac6557e246cf78d6d00fa42a6e0e8f 100644 (file)
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
 static bool check_access(DisasContext *ctx)
 {
     if (!ctx->hlsx) {
+        tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+                       offsetof(CPURISCVState, bins));
         if (ctx->virt_enabled) {
             generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
         } else {