return -EBUSY;
 }
 
+static int mid_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
+{
+       dws->rxchan = dma_request_slave_channel(dev, "rx");
+       if (!dws->rxchan)
+               return -ENODEV;
+       dws->master->dma_rx = dws->rxchan;
+
+       dws->txchan = dma_request_slave_channel(dev, "tx");
+       if (!dws->txchan) {
+               dma_release_channel(dws->rxchan);
+               return -ENODEV;
+       }
+       dws->master->dma_tx = dws->txchan;
+
+       dws->dma_inited = 1;
+       return 0;
+}
+
 static void mid_spi_dma_exit(struct dw_spi *dws)
 {
        if (!dws->dma_inited)
        dws->dma_rx = &mid_dma_rx;
        dws->dma_ops = &mfld_dma_ops;
 }
+
+static const struct dw_spi_dma_ops generic_dma_ops = {
+       .dma_init       = mid_spi_dma_init_generic,
+       .dma_exit       = mid_spi_dma_exit,
+       .dma_setup      = mid_spi_dma_setup,
+       .can_dma        = mid_spi_can_dma,
+       .dma_transfer   = mid_spi_dma_transfer,
+       .dma_stop       = mid_spi_dma_stop,
+};
+
+static void dw_spi_mid_setup_dma_generic(struct dw_spi *dws)
+{
+       dws->dma_tx = &mid_dma_tx;
+       dws->dma_rx = &mid_dma_rx;
+       dws->dma_ops = &generic_dma_ops;
+}
 #else  /* CONFIG_SPI_DW_MID_DMA */
 static inline void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) {}
+static inline void dw_spi_mid_setup_dma_generic(struct dw_spi *dws) {}
 #endif
 
 /* Some specific info for SPI0 controller on Intel MID */
        dw_spi_mid_setup_dma_mfld(dws);
        return 0;
 }
+
+int dw_spi_mid_init_generic(struct dw_spi *dws)
+{
+       /* Register hook to configure CTRLR0 */
+       dws->update_cr0 = dw_spi_update_cr0;
+
+       dw_spi_mid_setup_dma_generic(dws);
+       return 0;
+}