arm64: zynqmp: Assign TSU clock frequency for GEMs

Allow changing TSU clock for all GEMs. Kria SOM is using this
functionality that's why set TSU clock frequency as 250MHz (minimum when
running at 1G) to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b9285b50a2a4abb136ecb0873343a4e84626581.1686228675.git.michal.simek@amd.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index f04716841a0c0e65dc4c3ed18884c5a381511bbf..ccaca29200bb93519432a7983ca6bb9f4acf3280 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -146,24 +146,28 @@
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
                 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem1 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
                 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem2 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
                 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem3 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
                 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gpio {

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
index e06c6824dea478ace441aa1e4f3cff0fa1ecbebd..ae1b9b2bdbee27fdf649f4ee69b75d3ddb6a9573 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -145,6 +145,7 @@
        pinctrl-0 = <&pinctrl_gem3_default>;
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       assigned-clock-rates = <250000000>;
 
        mdio: mdio {
                #address-cells = <1>;

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
index 030e2c93f0e6b59b85937d41dd272e7975abe7e0..b59e48be6465a5e0243d48736c10d17c7d918542 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -128,6 +128,7 @@
        pinctrl-0 = <&pinctrl_gem3_default>;
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       assigned-clock-rates = <250000000>;
 
        mdio: mdio {
                #address-cells = <1>;