arm64: zynqmp: Align usb clock nodes with binding
authorMichal Simek <michal.simek@amd.com>
Mon, 8 Jan 2024 15:39:25 +0000 (16:39 +0100)
committerMichal Simek <michal.simek@amd.com>
Mon, 22 Jan 2024 13:13:01 +0000 (14:13 +0100)
dwc3-xilinx.yaml defines 2 clocks which are not defined that's why define
them (bus_early clock is moved to bus_clk in glue logic).
With also describing kv260 assigned clock rates with assigned clocks.
Also add missing status property to standard dwc3 core.

Link: https://lore.kernel.org/r/aa4c65a8997c7a65f23da3a3088bb5eb64281307.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index ca1248784f59239e7bc91aa8f6ee8149da4ad513..dd4569e7bd95801197b602aeda74b278f784c855 100644 (file)
        assigned-clocks = <&zynqmp_clk UART1_REF>;
 };
 
-&dwc3_0 {
+&usb0 {
        clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
-&dwc3_1 {
+&dwc3_0 {
+       clocks = <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&usb1 {
        clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&dwc3_1 {
+       clocks = <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &watchdog0 {
index 9e5853206eeb76eaa34edbc9421f635e0a81cb0b..a7b8fffad49936b505f6ae2d6264bbb6213baeff 100644 (file)
@@ -94,6 +94,7 @@
        pinctrl-0 = <&pinctrl_usb0_default>;
        phy-names = "usb3-phy";
        phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+       assigned-clock-rates = <250000000>, <20000000>;
 };
 
 &dwc3_0 {
index be35c2c071712fe72d19ae436462ae6b1f31c7c7..25d20d8032305d1f922c3cbb28b9705bcd4b1e57 100644 (file)
                        status = "disabled";
                        compatible = "xlnx,zynqmp-dwc3";
                        reg = <0x0 0xff9d0000 0x0 0x100>;
+                       clock-names = "bus_clk", "ref_clk";
                        power-domains = <&zynqmp_firmware PD_USB_0>;
                        resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
                                 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 
                        dwc3_0: usb@fe200000 {
                                compatible = "snps,dwc3";
+                               status = "disabled";
                                reg = <0x0 0xfe200000 0x0 0x40000>;
                                interrupt-parent = <&gic>;
                                interrupt-names = "host", "peripheral", "otg";
                                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                               clock-names = "bus_early", "ref";
+                               clock-names = "ref";
                                /* iommus = <&smmu 0x860>; */
                                snps,quirk-frame-length-adjustment = <0x20>;
                                snps,resume-hs-terminations;
                        status = "disabled";
                        compatible = "xlnx,zynqmp-dwc3";
                        reg = <0x0 0xff9e0000 0x0 0x100>;
+                       clock-names = "bus_clk", "ref_clk";
                        power-domains = <&zynqmp_firmware PD_USB_1>;
                        resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
                                 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 
                        dwc3_1: usb@fe300000 {
                                compatible = "snps,dwc3";
+                               status = "disabled";
                                reg = <0x0 0xfe300000 0x0 0x40000>;
                                interrupt-parent = <&gic>;
                                interrupt-names = "host", "peripheral", "otg";
                                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                               clock-names = "bus_early", "ref";
+                               clock-names = "ref";
                                /* iommus = <&smmu 0x861>; */
                                snps,quirk-frame-length-adjustment = <0x20>;
                                snps,resume-hs-terminations;