ARM: dts: r8a7745: Add QSPI support

Add the DT node for the QSPI interface to the SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index adf30890cb07de0cc55af65d7640693fea4295fc..5cc4009c426532c26f0172956067b4c2765ca986 100644 (file)
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -25,6 +25,7 @@
                i2c3 = &i2c3;
                i2c4 = &i2c4;
                i2c5 = &i2c5;
+               spi0 = &qspi;
        };
 
        cpus {
@@ -736,6 +737,22 @@
                        status = "disabled";
                };
 
+               qspi: spi@e6b10000 {
+                       compatible = "renesas,qspi-r8a7745", "renesas,qspi";
+                       reg = <0 0xe6b10000 0 0x2c>;
+                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                              <&dmac1 0x17>, <&dmac1 0x18>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       resets = <&cpg 917>;
+                       status = "disabled";
+               };
+
                sdhi0: sd@ee100000 {
                        compatible = "renesas,sdhi-r8a7745";
                        reg = <0 0xee100000 0 0x328>;