drm/amd/display: insert drv-pmfw log + rollback to new context

Rollback to new context for active display: this was previous tested
sequence. Avoid to do OTG master toggle is no active display at all,
this w/a was for fifo err.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index d5fde7d23fbf8e273e349a1bfdfb58fdfad3de7d..9e0fa01ecb795619c3d920306e1634e2c13bb674 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -80,12 +80,12 @@
 
 static int dcn35_get_active_display_cnt_wa(
                struct dc *dc,
-               struct dc_state *context)
+               struct dc_state *context,
+               int *all_active_disps)
 {
-       int i, display_count;
+       int i, display_count = 0;
        bool tmds_present = false;
 
-       display_count = 0;
        for (i = 0; i < context->stream_count; i++) {
                const struct dc_stream_state *stream = context->streams[i];
 
@@ -103,7 +103,8 @@ static int dcn35_get_active_display_cnt_wa(
                                link->link_enc->funcs->is_dig_enabled(link->link_enc))
                        display_count++;
        }
-
+       if (all_active_disps != NULL)
+               *all_active_disps = display_count;
        /* WA for hang on HDMI after display off back on*/
        if (display_count == 0 && tmds_present)
                display_count = 1;
@@ -224,15 +225,16 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
        struct dc *dc = clk_mgr_base->ctx->dc;
-       int display_count;
+       int display_count = 0;
        bool update_dppclk = false;
        bool update_dispclk = false;
        bool dpp_clock_lowered = false;
+       int all_active_disps = 0;
 
        if (dc->work_arounds.skip_clock_update)
                return;
 
-       /* DTBCLK is fixed, so set a default if unspecified. */
+       display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
        if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
                new_clocks->ref_dtbclk_khz = 600000;
 
@@ -254,7 +256,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
                }
                /* check that we're not already in lower */
                if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
-                       display_count = dcn35_get_active_display_cnt_wa(dc, context);
                        /* if we can go lower, go lower */
                        if (display_count == 0)
                                clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
@@ -311,11 +312,13 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
        }
 
        if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
-               dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
-
                clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
-               dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
-               dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
+               if (all_active_disps != 0) {
+                       dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
+                       dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+                       dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
+               } else
+                       dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 
                update_dispclk = true;
        }
@@ -826,7 +829,7 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
        struct dc_state *context = dc->current_state;
 
        if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
-               display_count = dcn35_get_active_display_cnt_wa(dc, context);
+               display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
                /* if we can go lower, go lower */
                if (display_count == 0)
                        clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index af0a0f2925950629113a075f9a1ad35079ac4856..786b62ab8d0fca3d55daf91f8cd24d315c733f05 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -279,7 +279,7 @@ void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, u
                clk_mgr,
                VBIOSSMC_MSG_SetDisplayIdleOptimizations,
                idle_info);
-       smu_print("VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info  = %d\n", idle_info);
+       smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info  = %x\n", __func__, idle_info);
 }
 
 void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
@@ -298,7 +298,7 @@ void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool e
                        clk_mgr,
                        VBIOSSMC_MSG_SetDisplayIdleOptimizations,
                        idle_info.data);
-       smu_print("dcn35_smu_enable_phy_refclk_pwrdwn  = %d\n", enable ? 1 : 0);
+       smu_print("%s smu_enable_phy_refclk_pwrdwn  = %d\n", __func__, enable ? 1 : 0);
 }
 
 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
@@ -310,6 +310,7 @@ void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
                        clk_mgr,
                        VBIOSSMC_MSG_UpdatePmeRestore,
                        0);
+       smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__);
 }
 
 void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
@@ -350,7 +351,7 @@ void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 
 void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)
 {
-       unsigned int msg_id, param;
+       unsigned int msg_id, param, retv;
 
        if (!clk_mgr->smu_present)
                return;
@@ -360,27 +361,32 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
        case DCN_ZSTATE_SUPPORT_ALLOW:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10) | (1 << 9) | (1 << 8);
+               smu_print("%s: SMC_MSG_AllowZstatesEntr msg = ALLOW, param = %d\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_DISALLOW:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = 0;
+               smu_print("%s: SMC_MSG_AllowZstatesEntr msg_id = DISALLOW, param = %d\n",  __func__, param);
                break;
 
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10);
+               smu_print("%s: SMC_MSG_AllowZstatesEntr msg = ALLOW_Z10_ONLY, param = %d\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10) | (1 << 8);
+               smu_print("%s: SMC_MSG_AllowZstatesEntr msg = ALLOW_Z8_Z10_ONLY, param = %d\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 8);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = %d\n", __func__, param);
                break;
 
        default: //DCN_ZSTATE_SUPPORT_UNKNOWN
@@ -390,11 +396,11 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
        }
 
 
-       dcn35_smu_send_msg_with_param(
+       retv = dcn35_smu_send_msg_with_param(
                clk_mgr,
                msg_id,
                param);
-       smu_print("dcn35_smu_set_zstate_support msg_id = %d, param = %d\n", msg_id, param);
+       smu_print("%s:  msg_id = %d, param = 0x%x, return = %d\n", __func__, msg_id, param, retv);
 }
 
 int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
@@ -408,7 +414,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
                                                 VBIOSSMC_MSG_GetDprefclkFreq,
                                                 0);
 
-       smu_print("dcn35_smu_get_DPREF clk  = %d mhz\n", dprefclk);
+       smu_print("%s:  SMU DPREF clk  = %d mhz\n",  __func__, dprefclk);
        return dprefclk * 1000;
 }
 
@@ -423,7 +429,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
                                               VBIOSSMC_MSG_GetDtbclkFreq,
                                               0);
 
-       smu_print("dcn35_smu_get_dtbclk  = %d mhz\n", dtbclk);
+       smu_print("%s: get_dtbclk  = %dmhz\n", __func__, dtbclk);
        return dtbclk * 1000;
 }
 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
@@ -436,7 +442,7 @@ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
                        clk_mgr,
                        VBIOSSMC_MSG_SetDtbClk,
                        enable);
-       smu_print("dcn35_smu_set_dtbclk  = %d \n", enable ? 1 : 0);
+       smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);
 }
 
 void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
@@ -445,30 +451,45 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl
                        clk_mgr,
                        VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
                        enable);
+       smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);
 }
 
 int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
 {
-       return dcn35_smu_send_msg_with_param(
+       int retv;
+
+       retv = dcn35_smu_send_msg_with_param(
                clk_mgr,
                VBIOSSMC_MSG_DispPsrExit,
                0);
+       smu_print("%s: smu_exit_low_power_state return = %d\n", __func__, retv);
+       return retv;
 }
 
 int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
 {
-       return dcn35_smu_send_msg_with_param(
+       int retv;
+
+       retv = dcn35_smu_send_msg_with_param(
                        clk_mgr,
                        VBIOSSMC_MSG_QueryIPS2Support,
                        0);
+
+       smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);
+       return retv;
 }
 
 void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
 {
        REG_WRITE(MP1_SMN_C2PMSG_71, param);
+       smu_print("%s: write_ips_scratch = %x\n", __func__, param);
 }
 
 uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
 {
-       return REG_READ(MP1_SMN_C2PMSG_71);
+       uint32_t retv;
+
+       retv = REG_READ(MP1_SMN_C2PMSG_71);
+       smu_print("%s: dcn35_smu_read_ips_scratch = %x\n",  __func__, retv);
+       return retv;
 }