drm/msm/a6xx: Add missing regs for A7XX

Add some missing definitions required for A7 support.

This may be substituted with a mesa header sync.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/559282/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index 1c051535fd4ab1825da7c6c75967dc74bf2ae8ec..863b5e3b0e67db211295d3e2a9215b98fe533088 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1114,6 +1114,12 @@ enum a6xx_tex_type {
 #define REG_A6XX_CP_MISC_CNTL                                  0x00000840
 
 #define REG_A6XX_CP_APRIV_CNTL                                 0x00000844
+#define A6XX_CP_APRIV_CNTL_CDWRITE                             0x00000040
+#define A6XX_CP_APRIV_CNTL_CDREAD                              0x00000020
+#define A6XX_CP_APRIV_CNTL_RBRPWB                              0x00000008
+#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL                         0x00000004
+#define A6XX_CP_APRIV_CNTL_RBFETCH                             0x00000002
+#define A6XX_CP_APRIV_CNTL_ICACHE                              0x00000001
 
 #define REG_A6XX_CP_PREEMPT_THRESHOLD                          0x000008c0
 
@@ -1939,6 +1945,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
 
 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE                      0x00000122
 
+#define REG_A7XX_RBBM_CLOCK_HYST2_VFD                          0x0000012f
+
 #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL                        0x000005ff
 
 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A                         0x00000600
@@ -8252,5 +8260,6 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
 
 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1                   0x00000002
 
+#define REG_A7XX_CX_MISC_TCM_RET_CNTL                          0x00000039
 
 #endif /* A6XX_XML */

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
index fcd9eb53baf8d1d0a9535f63ca29546cadfcb547..5b66efafc901b0cba2b15de95ed1c34e354291c0 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
@@ -360,6 +360,12 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
 
 #define REG_A6XX_GMU_GENERAL_7                                 0x000051cc
 
+#define REG_A6XX_GMU_GENERAL_8                                 0x000051cd
+
+#define REG_A6XX_GMU_GENERAL_9                                 0x000051ce
+
+#define REG_A6XX_GMU_GENERAL_10                                        0x000051cf
+
 #define REG_A6XX_GMU_ISENSE_CTRL                               0x0000515d
 
 #define REG_A6XX_GPU_CS_ENABLE_REG                             0x00008920
@@ -471,6 +477,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
 
 #define REG_A6XX_RSCC_SEQ_BUSY_DRV0                            0x00000101
 
+#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740                      0x00000154
+
 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0                           0x00000180
 
 #define REG_A6XX_RSCC_TCS0_DRV0_STATUS                         0x00000346