return 0;
 }
 
+static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
+               struct sas_phy_linkrates *r)
+{
+       u32 prog_phy_link_rate =
+               hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
+       struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+       struct asd_sas_phy *sas_phy = &phy->sas_phy;
+       int i;
+       enum sas_linkrate min, max;
+       u32 rate_mask = 0;
+
+       if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
+               max = sas_phy->phy->maximum_linkrate;
+               min = r->minimum_linkrate;
+       } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
+               max = r->maximum_linkrate;
+               min = sas_phy->phy->minimum_linkrate;
+       } else
+               return;
+
+       sas_phy->phy->maximum_linkrate = max;
+       sas_phy->phy->minimum_linkrate = min;
+
+       min -= SAS_LINK_RATE_1_5_GBPS;
+       max -= SAS_LINK_RATE_1_5_GBPS;
+
+       for (i = 0; i <= max; i++)
+               rate_mask |= 1 << (i * 2);
+
+       prog_phy_link_rate &= ~0xff;
+       prog_phy_link_rate |= rate_mask;
+
+       hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
+                       prog_phy_link_rate);
+
+       phy_hard_reset_v3_hw(hisi_hba, phy_no);
+}
+
 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
 {
        struct pci_dev *pdev = hisi_hba->pci_dev;
        .phy_disable = disable_phy_v3_hw,
        .phy_hard_reset = phy_hard_reset_v3_hw,
        .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
+       .phy_set_linkrate = phy_set_linkrate_v3_hw,
        .dereg_device = dereg_device_v3_hw,
        .soft_reset = soft_reset_v3_hw,
        .get_phys_state = get_phys_state_v3_hw,