#define CEC_CLOCK_FREQ 40000
 #define VC4_HSM_MID_CLOCK 149985000
 
+#define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
+
 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 {
        struct drm_info_node *node = (struct drm_info_node *)m->private;
        .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
        .debugfs_name           = "hdmi0_regs",
        .card_name              = "vc4-hdmi-0",
-       .max_pixel_clock        = 297000000,
+       .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
        .registers              = vc5_hdmi_hdmi0_fields,
        .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
        .phy_lane_mapping       = {
        .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
        .debugfs_name           = "hdmi1_regs",
        .card_name              = "vc4-hdmi-1",
-       .max_pixel_clock        = 297000000,
+       .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
        .registers              = vc5_hdmi_hdmi1_fields,
        .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
        .phy_lane_mapping       = {