#define ICE_PHY_TYPE_HIGH_100G_CAUI2           BIT_ULL(2)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC    BIT_ULL(3)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2            BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX            4
+#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4                BIT_ULL(5)
+#define ICE_PHY_TYPE_HIGH_200G_SR4             BIT_ULL(6)
+#define ICE_PHY_TYPE_HIGH_200G_FR4             BIT_ULL(7)
+#define ICE_PHY_TYPE_HIGH_200G_LR4             BIT_ULL(8)
+#define ICE_PHY_TYPE_HIGH_200G_DR4             BIT_ULL(9)
+#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4                BIT_ULL(10)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC    BIT_ULL(11)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4            BIT_ULL(12)
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX            12
 
 struct ice_aqc_get_phy_caps_data {
        __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
 #define ICE_AQ_LINK_SPEED_40GB         BIT(8)
 #define ICE_AQ_LINK_SPEED_50GB         BIT(9)
 #define ICE_AQ_LINK_SPEED_100GB                BIT(10)
+#define ICE_AQ_LINK_SPEED_200GB                BIT(11)
 #define ICE_AQ_LINK_SPEED_UNKNOWN      BIT(15)
        __le32 reserved3; /* Aligns next field to 8-byte boundary */
        __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
 
        ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
 };
 
+static const u32 ice_adv_lnk_speed_200000[] __initconst = {
+       ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
+};
+
 static struct ethtool_forced_speed_map ice_adv_lnk_speed_maps[] __ro_after_init = {
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 1000),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 40000),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 50000),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100000),
+       ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 200000),
 };
 
 void __init ice_adv_lnk_speed_maps_init(void)
                                         ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \
                                         ICE_PHY_TYPE_HIGH_100G_AUI2)
 
+#define ICE_PHY_TYPE_HIGH_MASK_200G    (ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_SR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_FR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_LR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_DR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \
+                                        ICE_PHY_TYPE_HIGH_200G_AUI4)
+
 /**
  * ice_mask_min_supported_speeds
  * @hw: pointer to the HW structure
                              u64 phy_types_high, u64 *phy_types_low)
 {
        /* if QSFP connection with 100G speed, minimum supported speed is 25G */
-       if (*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G ||
-           phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G)
+       if ((*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G) ||
+           (phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G) ||
+           (phy_types_high & ICE_PHY_TYPE_HIGH_MASK_200G))
                *phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_25G;
        else if (!ice_is_100m_speed_supported(hw))
                *phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;
        ice_phy_type_to_ethtool(netdev, ks);
 
        switch (link_info->link_speed) {
+       case ICE_AQ_LINK_SPEED_200GB:
+               ks->base.speed = SPEED_200000;
+               break;
        case ICE_AQ_LINK_SPEED_100GB:
                ks->base.speed = SPEED_100000;
                break;
 
        [2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
        [3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
        [4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
+       [5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
+       [6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
+       [7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
+       [8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
+       [9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full),
+       [10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),
+       [11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
+       [12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
 };
 
 #endif /* !_ICE_ETHTOOL_H_ */