ice: Add 200G speed/phy type use
authorAlice Michael <alice.michael@intel.com>
Wed, 25 Oct 2023 21:41:53 +0000 (14:41 -0700)
committerJakub Kicinski <kuba@kernel.org>
Fri, 27 Oct 2023 03:32:38 +0000 (20:32 -0700)
Add the support for 200G phy speeds and the mapping for their
advertisement in link. Add the new PHY type bits for AQ command, as
needed for 200G E830 controllers.

Signed-off-by: Alice Michael <alice.michael@intel.com>
Co-developed-by: Pawel Chmielewski <pawel.chmielewski@intel.com>
Signed-off-by: Pawel Chmielewski <pawel.chmielewski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Tested-by: Tony Brelinski <tony.brelinski@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20231025214157.1222758-3-jacob.e.keller@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
drivers/net/ethernet/intel/ice/ice_common.c
drivers/net/ethernet/intel/ice/ice_ethtool.c
drivers/net/ethernet/intel/ice/ice_ethtool.h

index 51281b58ad720f1af407cf8545f89ae5a15be7af..ee9acd19505df1797168fb2ba8f8b9cb3f89aada 100644 (file)
@@ -1099,7 +1099,15 @@ struct ice_aqc_get_phy_caps {
 #define ICE_PHY_TYPE_HIGH_100G_CAUI2           BIT_ULL(2)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC    BIT_ULL(3)
 #define ICE_PHY_TYPE_HIGH_100G_AUI2            BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX            4
+#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4                BIT_ULL(5)
+#define ICE_PHY_TYPE_HIGH_200G_SR4             BIT_ULL(6)
+#define ICE_PHY_TYPE_HIGH_200G_FR4             BIT_ULL(7)
+#define ICE_PHY_TYPE_HIGH_200G_LR4             BIT_ULL(8)
+#define ICE_PHY_TYPE_HIGH_200G_DR4             BIT_ULL(9)
+#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4                BIT_ULL(10)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC    BIT_ULL(11)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4            BIT_ULL(12)
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX            12
 
 struct ice_aqc_get_phy_caps_data {
        __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
@@ -1319,6 +1327,7 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_SPEED_40GB         BIT(8)
 #define ICE_AQ_LINK_SPEED_50GB         BIT(9)
 #define ICE_AQ_LINK_SPEED_100GB                BIT(10)
+#define ICE_AQ_LINK_SPEED_200GB                BIT(11)
 #define ICE_AQ_LINK_SPEED_UNKNOWN      BIT(15)
        __le32 reserved3; /* Aligns next field to 8-byte boundary */
        __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
index 683a0d6b533751391b2e7171d7a8ef3d494df218..4875d59f27f24f947d97a86553cf263de395d710 100644 (file)
@@ -6092,6 +6092,7 @@ static const u32 ice_aq_to_link_speed[] = {
        SPEED_40000,
        SPEED_50000,
        SPEED_100000,   /* BIT(10) */
+       SPEED_200000,
 };
 
 /**
index 7870a39845473682e0271ebb0a51af16b2672232..a34083567e6ff556b590c20fc28fd9196cb1acd9 100644 (file)
@@ -400,6 +400,14 @@ static const u32 ice_adv_lnk_speed_100000[] __initconst = {
        ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
 };
 
+static const u32 ice_adv_lnk_speed_200000[] __initconst = {
+       ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
+       ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
+};
+
 static struct ethtool_forced_speed_map ice_adv_lnk_speed_maps[] __ro_after_init = {
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 1000),
@@ -410,6 +418,7 @@ static struct ethtool_forced_speed_map ice_adv_lnk_speed_maps[] __ro_after_init
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 40000),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 50000),
        ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100000),
+       ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 200000),
 };
 
 void __init ice_adv_lnk_speed_maps_init(void)
@@ -1712,6 +1721,15 @@ ice_get_ethtool_stats(struct net_device *netdev,
                                         ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \
                                         ICE_PHY_TYPE_HIGH_100G_AUI2)
 
+#define ICE_PHY_TYPE_HIGH_MASK_200G    (ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_SR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_FR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_LR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_DR4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 | \
+                                        ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \
+                                        ICE_PHY_TYPE_HIGH_200G_AUI4)
+
 /**
  * ice_mask_min_supported_speeds
  * @hw: pointer to the HW structure
@@ -1726,8 +1744,9 @@ ice_mask_min_supported_speeds(struct ice_hw *hw,
                              u64 phy_types_high, u64 *phy_types_low)
 {
        /* if QSFP connection with 100G speed, minimum supported speed is 25G */
-       if (*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G ||
-           phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G)
+       if ((*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G) ||
+           (phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G) ||
+           (phy_types_high & ICE_PHY_TYPE_HIGH_MASK_200G))
                *phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_25G;
        else if (!ice_is_100m_speed_supported(hw))
                *phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;
@@ -1870,6 +1889,9 @@ ice_get_settings_link_up(struct ethtool_link_ksettings *ks,
        ice_phy_type_to_ethtool(netdev, ks);
 
        switch (link_info->link_speed) {
+       case ICE_AQ_LINK_SPEED_200GB:
+               ks->base.speed = SPEED_200000;
+               break;
        case ICE_AQ_LINK_SPEED_100GB:
                ks->base.speed = SPEED_100000;
                break;
index b403ee79cd5e47482b86b5fde24c55c7f972e4bb..b88e3da06f13d0bad3cdfa651ef06be40798e8d0 100644 (file)
@@ -100,6 +100,14 @@ phy_type_high_lkup[] = {
        [2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
        [3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
        [4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
+       [5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
+       [6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
+       [7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
+       [8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
+       [9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full),
+       [10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),
+       [11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
+       [12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
 };
 
 #endif /* !_ICE_ETHTOOL_H_ */