dmaengine: idxd: process batch descriptor completion record faults

Add event log processing for faulting of user batch descriptor completion
record.

When encountering an event log entry for a page fault on a completion
record, the driver is expected to do the following:
1. If the "first error in batch" bit in event log entry error info is
set, discard any previously recorded errors associated with the
"batch identifier".
2. Fix the page fault according to the fault address in the event log. If
successful, write the completion record to the fault address in user space.
3. If an error is encountered while writing the completion record and it is
associated to a descriptor in the batch, the driver associates the error
with the batch identifier of the event log entry and tracks it until the
event log entry for the corresponding batch desc is encountered.

While processing an event log entry for a batch descriptor with error
indicating that one or more descs in the batch had event log entries,
the driver will do the following before writing the batch completion
record:
1. If the status field of the completion record is 0x1, the driver will
change it to error code 0x5 (one or more operations in batch completed
with status not successful) and changes the result field to 1.
2. If the status is error code 0x6 (page fault on batch descriptor list
address), change the result field to 1.
3. If status is any other value, the completion record is not changed.
4. Clear the recorded error in preparation for next batch with same batch
identifier.

The result field is for user software to determine whether to set the
"Batch Error" flag bit in the descriptor for continuation of partial
batch descriptor completion. See DSA spec 2.0 for additional information.

If no error has been recorded for the batch, the batch completion record is
written to user space as is.

Tested-by: Tony Zhu <tony.zhu@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20230407203143.2189681-12-fenghua.yu@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h
index 3963c83165a66626f95b37679a9c9952002f44f4..4c4baa80c731ce02ce92c70d7545a035f25eff91 100644 (file)
--- a/drivers/dma/idxd/idxd.h
+++ b/drivers/dma/idxd/idxd.h
@@ -265,6 +265,8 @@ struct idxd_driver_data {
        int compl_size;
        int align;
        int evl_cr_off;
+       int cr_status_off;
+       int cr_result_off;
 };
 
 struct idxd_evl {
@@ -278,6 +280,7 @@ struct idxd_evl {
        u16 size;
        u16 head;
        unsigned long *bmap;
+       bool batch_fail[IDXD_MAX_BATCH_IDENT];
 };
 
 struct idxd_evl_fault {

diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
index 18344593b83fc3480eabc49ff12585eed30c98fa..92f60d3643920355b7449fc44716d7e88ae86048 100644 (file)
--- a/drivers/dma/idxd/init.c
+++ b/drivers/dma/idxd/init.c
@@ -47,6 +47,8 @@ static struct idxd_driver_data idxd_driver_data[] = {
                .align = 32,
                .dev_type = &dsa_device_type,
                .evl_cr_off = offsetof(struct dsa_evl_entry, cr),
+               .cr_status_off = offsetof(struct dsa_completion_record, status),
+               .cr_result_off = offsetof(struct dsa_completion_record, result),
        },
        [IDXD_TYPE_IAX] = {
                .name_prefix = "iax",
@@ -55,6 +57,8 @@ static struct idxd_driver_data idxd_driver_data[] = {
                .align = 64,
                .dev_type = &iax_device_type,
                .evl_cr_off = offsetof(struct iax_evl_entry, cr),
+               .cr_status_off = offsetof(struct iax_completion_record, status),
+               .cr_result_off = offsetof(struct iax_completion_record, error_code),
        },
 };
 

diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c
index 96983975f974c7c560623ecee2d7be3821efdb15..c660d63a3eb8d5b8b6cd5da12e57b20e0235258a 100644 (file)
--- a/drivers/dma/idxd/irq.c
+++ b/drivers/dma/idxd/irq.c
@@ -225,37 +225,79 @@ static void idxd_evl_fault_work(struct work_struct *work)
        struct idxd_wq *wq = fault->wq;
        struct idxd_device *idxd = wq->idxd;
        struct device *dev = &idxd->pdev->dev;
+       struct idxd_evl *evl = idxd->evl;
        struct __evl_entry *entry_head = fault->entry;
        void *cr = (void *)entry_head + idxd->data->evl_cr_off;
-       int cr_size = idxd->data->compl_size, copied;
+       int cr_size = idxd->data->compl_size;
+       u8 *status = (u8 *)cr + idxd->data->cr_status_off;
+       u8 *result = (u8 *)cr + idxd->data->cr_result_off;
+       int copied, copy_size;
+       bool *bf;
 
        switch (fault->status) {
        case DSA_COMP_CRA_XLAT:
-       case DSA_COMP_DRAIN_EVL:
-               /*
-                * Copy completion record to fault_addr in user address space
-                * that is found by wq and PASID.
-                */
-               copied = idxd_copy_cr(wq, entry_head->pasid,
-                                     entry_head->fault_addr,
-                                     cr, cr_size);
-               /*
-                * The task that triggered the page fault is unknown currently
-                * because multiple threads may share the user address
-                * space or the task exits already before this fault.
-                * So if the copy fails, SIGSEGV can not be sent to the task.
-                * Just print an error for the failure. The user application
-                * waiting for the completion record will time out on this
-                * failure.
-                */
-               if (copied != cr_size) {
-                       dev_dbg_ratelimited(dev, "Failed to write to completion record. (%d:%d)\n",
-                                           cr_size, copied);
+               if (entry_head->batch && entry_head->first_err_in_batch)
+                       evl->batch_fail[entry_head->batch_id] = false;
+
+               copy_size = cr_size;
+               break;
+       case DSA_COMP_BATCH_EVL_ERR:
+               bf = &evl->batch_fail[entry_head->batch_id];
+
+               copy_size = entry_head->rcr || *bf ? cr_size : 0;
+               if (*bf) {
+                       if (*status == DSA_COMP_SUCCESS)
+                               *status = DSA_COMP_BATCH_FAIL;
+                       *result = 1;
+                       *bf = false;
                }
                break;
+       case DSA_COMP_DRAIN_EVL:
+               copy_size = cr_size;
+               break;
        default:
-               dev_dbg_ratelimited(dev, "Unrecognized error code: %#x\n",
-                                   DSA_COMP_STATUS(entry_head->error));
+               copy_size = 0;
+               dev_dbg_ratelimited(dev, "Unrecognized error code: %#x\n", fault->status);
+               break;
+       }
+
+       if (copy_size == 0)
+               return;
+
+       /*
+        * Copy completion record to fault_addr in user address space
+        * that is found by wq and PASID.
+        */
+       copied = idxd_copy_cr(wq, entry_head->pasid, entry_head->fault_addr,
+                             cr, copy_size);
+       /*
+        * The task that triggered the page fault is unknown currently
+        * because multiple threads may share the user address
+        * space or the task exits already before this fault.
+        * So if the copy fails, SIGSEGV can not be sent to the task.
+        * Just print an error for the failure. The user application
+        * waiting for the completion record will time out on this
+        * failure.
+        */
+       switch (fault->status) {
+       case DSA_COMP_CRA_XLAT:
+               if (copied != copy_size) {
+                       dev_dbg_ratelimited(dev, "Failed to write to completion record: (%d:%d)\n",
+                                           copy_size, copied);
+                       if (entry_head->batch)
+                               evl->batch_fail[entry_head->batch_id] = true;
+               }
+               break;
+       case DSA_COMP_BATCH_EVL_ERR:
+               if (copied != copy_size) {
+                       dev_dbg_ratelimited(dev, "Failed to write to batch completion record: (%d:%d)\n",
+                                           copy_size, copied);
+               }
+               break;
+       case DSA_COMP_DRAIN_EVL:
+               if (copied != copy_size)
+                       dev_dbg_ratelimited(dev, "Failed to write to drain completion record: (%d:%d)\n",
+                                           copy_size, copied);
                break;
        }
 
@@ -274,7 +316,8 @@ static void process_evl_entry(struct idxd_device *idxd,
        } else {
                status = DSA_COMP_STATUS(entry_head->error);
 
-               if (status == DSA_COMP_CRA_XLAT || status == DSA_COMP_DRAIN_EVL) {
+               if (status == DSA_COMP_CRA_XLAT || status == DSA_COMP_DRAIN_EVL ||
+                   status == DSA_COMP_BATCH_EVL_ERR) {
                        struct idxd_evl_fault *fault;
                        int ent_size = evl_ent_size(idxd);
 

diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
index 148db94f9373e933e626e0cd9fdaadd0a8e6b588..9f3959d001b60e3a9f7523f20854787ab92309a7 100644 (file)
--- a/drivers/dma/idxd/registers.h
+++ b/drivers/dma/idxd/registers.h
@@ -35,7 +35,7 @@ union gen_cap_reg {
                u64 drain_readback:1;
                u64 rsvd2:3;
                u64 evl_support:2;
-               u64 rsvd4:1;
+               u64 batch_continuation:1;
                u64 max_xfer_shift:5;
                u64 max_batch_shift:4;
                u64 max_ims_mult:6;
@@ -577,6 +577,8 @@ union evl_status_reg {
        u64 bits;
 } __packed;
 
+#define IDXD_MAX_BATCH_IDENT   256
+
 struct __evl_entry {
        u64 rsvd:2;
        u64 desc_valid:1;

diff --git a/include/uapi/linux/idxd.h b/include/uapi/linux/idxd.h
index 76ad71bf751e1aff2c8f54d64c77464f00421fc9..606b52e88ce335b02e3efa5a558fd3bba20481ab 100644 (file)
--- a/include/uapi/linux/idxd.h
+++ b/include/uapi/linux/idxd.h
@@ -136,6 +136,7 @@ enum dsa_completion_status {
        DSA_COMP_HW_ERR_DRB,
        DSA_COMP_TRANSLATION_FAIL,
        DSA_COMP_DRAIN_EVL = 0x26,
+       DSA_COMP_BATCH_EVL_ERR,
 };
 
 enum iax_completion_status {