+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * MPC8610 HPCD Device Tree Source
- *
- * Copyright 2007-2008 Freescale Semiconductor Inc.
- */
-
-/dts-v1/;
-
-/ {
- model = "MPC8610HPCD";
- compatible = "fsl,MPC8610HPCD";
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- pci0 = &pci0;
- pci1 = &pci1;
- pci2 = &pci2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8610@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <32768>; // L1
- i-cache-size = <32768>; // L1
- sleep = <&pmc 0x00008000 0 // core
- &pmc 0x00004000 0>; // timebase
- timebase-frequency = <0>; // From uboot
- bus-frequency = <0>; // From uboot
- clock-frequency = <0>; // From uboot
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; // 512M at 0x0
- };
-
- localbus@e0005000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
- reg = <0xe0005000 0x1000>;
- interrupts = <19 2>;
- interrupt-parent = <&mpic>;
- ranges = <0 0 0xf8000000 0x08000000
- 1 0 0xf0000000 0x08000000
- 2 0 0xe8400000 0x00008000
- 4 0 0xe8440000 0x00008000
- 5 0 0xe8480000 0x00008000
- 6 0 0xe84c0000 0x00008000
- 3 0 0xe8000000 0x00000020>;
- sleep = <&pmc 0x08000000 0>;
-
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- flash@1,0 {
- compatible = "cfi-flash";
- reg = <1 0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- flash@2,0 {
- compatible = "fsl,mpc8610-fcm-nand",
- "fsl,elbc-fcm-nand";
- reg = <2 0 0x8000>;
- };
-
- flash@4,0 {
- compatible = "fsl,mpc8610-fcm-nand",
- "fsl,elbc-fcm-nand";
- reg = <4 0 0x8000>;
- };
-
- flash@5,0 {
- compatible = "fsl,mpc8610-fcm-nand",
- "fsl,elbc-fcm-nand";
- reg = <5 0 0x8000>;
- };
-
- flash@6,0 {
- compatible = "fsl,mpc8610-fcm-nand",
- "fsl,elbc-fcm-nand";
- reg = <6 0 0x8000>;
- };
-
- board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,fpga-pixis";
- reg = <3 0 0x20>;
- ranges = <0 3 0 0x20>;
- interrupt-parent = <&mpic>;
- interrupts = <8 8>;
-
- sdcsr_pio: gpio-controller@a {
- #gpio-cells = <2>;
- compatible = "fsl,fpga-pixis-gpio-bank";
- reg = <0xa 1>;
- gpio-controller;
- };
- };
- };
-
- soc@e0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "soc";
- compatible = "fsl,mpc8610-immr", "simple-bus";
- ranges = <0x0 0xe0000000 0x00100000>;
- bus-frequency = <0>;
-
- mcm-law@0 {
- compatible = "fsl,mcm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <10>;
- };
-
- mcm@1000 {
- compatible = "fsl,mpc8610-mcm", "fsl,mcm";
- reg = <0x1000 0x1000>;
- interrupts = <17 2>;
- interrupt-parent = <&mpic>;
- };
-
- i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
-
- cs4270:codec@4f {
- compatible = "cirrus,cs4270";
- reg = <0x4f>;
- /* MCLK source is a stand-alone oscillator */
- clock-frequency = <12288000>;
- };
- };
-
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- sleep = <&pmc 0x00000004 0>;
- dfsrr;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- sleep = <&pmc 0x00000002 0>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- sleep = <&pmc 0x00000008 0>;
- };
-
- spi@7000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc8610-spi", "fsl,spi";
- reg = <0x7000 0x40>;
- cell-index = <0>;
- interrupts = <59 2>;
- interrupt-parent = <&mpic>;
- mode = "cpu";
- cs-gpios = <&sdcsr_pio 7 0>;
- sleep = <&pmc 0x00000800 0>;
-
- mmc-slot@0 {
- compatible = "fsl,mpc8610hpcd-mmc-slot",
- "mmc-spi-slot";
- reg = <0>;
- gpios = <&sdcsr_pio 0 1 /* nCD */
- &sdcsr_pio 1 0>; /* WP */
- voltage-ranges = <3300 3300>;
- spi-max-frequency = <50000000>;
- };
- };
-
- display@2c000 {
- compatible = "fsl,diu";
- reg = <0x2c000 100>;
- interrupts = <72 2>;
- interrupt-parent = <&mpic>;
- sleep = <&pmc 0x04000000 0>;
- };
-
- mpic: interrupt-controller@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
-
- msi@41600 {
- compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8610-guts";
- reg = <0xe0000 0x1000>;
- ranges = <0 0xe0000 0x1000>;
- fsl,has-rstcr;
-
- pmc: power@70 {
- compatible = "fsl,mpc8610-pmc",
- "fsl,mpc8641d-pmc";
- reg = <0x70 0x20>;
- };
- };
-
- wdt@e4000 {
- compatible = "fsl,mpc8610-wdt";
- reg = <0xe4000 0x100>;
- };
-
- ssi@16000 {
- compatible = "fsl,mpc8610-ssi";
- cell-index = <0>;
- reg = <0x16000 0x100>;
- interrupt-parent = <&mpic>;
- interrupts = <62 2>;
- fsl,mode = "i2s-slave";
- codec-handle = <&cs4270>;
- fsl,playback-dma = <&dma00>;
- fsl,capture-dma = <&dma01>;
- fsl,fifo-depth = <8>;
- sleep = <&pmc 0 0x08000000>;
- };
-
- ssi@16100 {
- compatible = "fsl,mpc8610-ssi";
- status = "disabled";
- cell-index = <1>;
- reg = <0x16100 0x100>;
- interrupt-parent = <&mpic>;
- interrupts = <63 2>;
- fsl,fifo-depth = <8>;
- sleep = <&pmc 0 0x04000000>;
- };
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
- cell-index = <0>;
- reg = <0x21300 0x4>; /* DMA general status register */
- ranges = <0x0 0x21100 0x200>;
- sleep = <&pmc 0x00000400 0>;
-
- dma00: dma-channel@0 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,ssi-dma-channel";
- cell-index = <0>;
- reg = <0x0 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma01: dma-channel@1 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,ssi-dma-channel";
- cell-index = <1>;
- reg = <0x80 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@2 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <2>;
- reg = <0x100 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@3 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <3>;
- reg = <0x180 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
- dma@c300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
- cell-index = <1>;
- reg = <0xc300 0x4>; /* DMA general status register */
- ranges = <0x0 0xc100 0x200>;
- sleep = <&pmc 0x00000200 0>;
-
- dma-channel@0 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <0>;
- reg = <0x0 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <76 2>;
- };
- dma-channel@1 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <1>;
- reg = <0x80 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <77 2>;
- };
- dma-channel@2 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <2>;
- reg = <0x100 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <78 2>;
- };
- dma-channel@3 {
- compatible = "fsl,mpc8610-dma-channel",
- "fsl,eloplus-dma-channel";
- cell-index = <3>;
- reg = <0x180 0x80>;
- interrupt-parent = <&mpic>;
- interrupts = <79 2>;
- };
- };
-
- };
-
- pci0: pci@e0008000 {
- compatible = "fsl,mpc8610-pci";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xe0008000 0x1000>;
- bus-range = <0 0>;
- ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
- 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
- sleep = <&pmc 0x80000000 0>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <24 2>;
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x11 */
- 0x8800 0 0 1 &mpic 4 1
- 0x8800 0 0 2 &mpic 5 1
- 0x8800 0 0 3 &mpic 6 1
- 0x8800 0 0 4 &mpic 7 1
-
- /* IDSEL 0x12 */
- 0x9000 0 0 1 &mpic 5 1
- 0x9000 0 0 2 &mpic 6 1
- 0x9000 0 0 3 &mpic 7 1
- 0x9000 0 0 4 &mpic 4 1
- >;
- };
-
- pci1: pcie@e000a000 {
- compatible = "fsl,mpc8641-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xe000a000 0x1000>;
- bus-range = <1 3>;
- ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
- 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
- sleep = <&pmc 0x40000000 0>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <26 2>;
- interrupt-map-mask = <0xf800 0 0 7>;
-
- interrupt-map = <
- /* IDSEL 0x1b */
- 0xd800 0 0 1 &mpic 2 1
-
- /* IDSEL 0x1c*/
- 0xe000 0 0 1 &mpic 1 1
- 0xe000 0 0 2 &mpic 1 1
- 0xe000 0 0 3 &mpic 1 1
- 0xe000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x1f */
- 0xf800 0 0 1 &mpic 3 2
- 0xf800 0 0 2 &mpic 0 1
- >;
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- ranges = <0x02000000 0x0 0xa0000000
- 0x02000000 0x0 0xa0000000
- 0x0 0x10000000
- 0x01000000 0x0 0x00000000
- 0x01000000 0x0 0x00000000
- 0x0 0x00100000>;
- uli1575@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <0x02000000 0x0 0xa0000000
- 0x02000000 0x0 0xa0000000
- 0x0 0x10000000
- 0x01000000 0x0 0x00000000
- 0x01000000 0x0 0x00000000
- 0x0 0x00100000>;
-
- isa@1e {
- device_type = "isa";
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <0xf000 0 0 0 0>;
- ranges = <1 0 0x01000000 0 0
- 0x00001000>;
-
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <1 0x70 2>;
- };
- };
- };
- };
- };
-
- pci2: pcie@e0009000 {
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- compatible = "fsl,mpc8641-pcie";
- reg = <0xe0009000 0x00001000>;
- ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
- 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
- bus-range = <0 255>;
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <0x0000 0 0 1 &mpic 4 1
- 0x0000 0 0 2 &mpic 5 1
- 0x0000 0 0 3 &mpic 6 1
- 0x0000 0 0 4 &mpic 7 1>;
- interrupt-parent = <&mpic>;
- interrupts = <25 2>;
- sleep = <&pmc 0x20000000 0>;
- clock-frequency = <33333333>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * MPC8610 HPCD board specific routines
- *
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
- * Recode: Jason Jin <jason.jin@freescale.com>
- * York Sun <yorksun@freescale.com>
- *
- * Rewrite the interrupt routing. remove the 8259PIC support,
- * All the integrated device in ULI use sideband interrupt.
- *
- * Copyright 2008 Freescale Semiconductor Inc.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/fsl/guts.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/udbg.h>
-
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_pci.h>
-#include <sysdev/fsl_soc.h>
-
-#include "mpc86xx.h"
-
-static struct device_node *pixis_node;
-static unsigned char *pixis_bdcfg0, *pixis_arch;
-
-/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
-#define CLKDVDR_PXCKEN 0x80000000
-#define CLKDVDR_PXCKINV 0x10000000
-#define CLKDVDR_PXCKDLY 0x06000000
-#define CLKDVDR_PXCLK_MASK 0x001F0000
-
-#ifdef CONFIG_SUSPEND
-static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
-{
- pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
- return IRQ_HANDLED;
-}
-
-static void __init mpc8610_suspend_init(void)
-{
- int irq;
- int ret;
-
- if (!pixis_node)
- return;
-
- irq = irq_of_parse_and_map(pixis_node, 0);
- if (!irq) {
- pr_err("%s: can't map pixis event IRQ.\n", __func__);
- return;
- }
-
- ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
- if (ret) {
- pr_err("%s: can't request pixis event IRQ: %d\n",
- __func__, ret);
- irq_dispose_mapping(irq);
- }
-
- enable_irq_wake(irq);
-}
-#else
-static inline void mpc8610_suspend_init(void) { }
-#endif /* CONFIG_SUSPEND */
-
-static const struct of_device_id mpc8610_ids[] __initconst = {
- { .compatible = "fsl,mpc8610-immr", },
- { .compatible = "fsl,mpc8610-guts", },
- /* So that the DMA channel nodes can be probed individually: */
- { .compatible = "fsl,eloplus-dma", },
- /* PCI controllers */
- { .compatible = "fsl,mpc8610-pci", },
- {}
-};
-
-static int __init mpc8610_declare_of_platform_devices(void)
-{
- /* Enable wakeup on PIXIS' event IRQ. */
- mpc8610_suspend_init();
-
- mpc86xx_common_publish_devices();
-
- /* Without this call, the SSI device driver won't get probed. */
- of_platform_bus_probe(NULL, mpc8610_ids, NULL);
-
- return 0;
-}
-machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
-
-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-
-/*
- * DIU Area Descriptor
- *
- * The MPC8610 reference manual shows the bits of the AD register in
- * little-endian order, which causes the BLUE_C field to be split into two
- * parts. To simplify the definition of the MAKE_AD() macro, we define the
- * fields in big-endian order and byte-swap the result.
- *
- * So even though the registers don't look like they're in the
- * same bit positions as they are on the P1022, the same value is written to
- * the AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_MASK 0x0E000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_MASK 0x01800000
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_MASK 0x00600000
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_MASK 0x00180000
-#define AD_RED_C_SHIFT 19
-#define AD_PALETTE 0x00040000
-#define AD_PIXEL_S_MASK 0x00030000
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_MASK 0x0000F000
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_MASK 0x00000F00
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_MASK 0x000000F0
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_MASK 0x0000000F
-#define AD_COMP_0_SHIFT 0
-
-#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
- cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
- (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
- (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
- (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
- (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
-
-u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
- unsigned int bits_per_pixel)
-{
- static const u32 pixelformat[][3] = {
- {
- MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
- MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
- MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
- },
- {
- MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
- MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
- MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
- },
- };
- unsigned int arch_monitor;
-
- /* The DVI port is mis-wired on revision 1 of this board. */
- arch_monitor =
- ((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
-
- switch (bits_per_pixel) {
- case 32:
- return pixelformat[arch_monitor][0];
- case 24:
- return pixelformat[arch_monitor][1];
- case 16:
- return pixelformat[arch_monitor][2];
- default:
- pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
- return 0;
- }
-}
-
-void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
- char *gamma_table_base)
-{
- int i;
- if (port == FSL_DIU_PORT_DLVDS) {
- for (i = 0; i < 256*3; i++)
- gamma_table_base[i] = (gamma_table_base[i] << 2) |
- ((gamma_table_base[i] >> 6) & 0x03);
- }
-}
-
-#define PX_BRDCFG0_DVISEL (1 << 3)
-#define PX_BRDCFG0_DLINK (1 << 4)
-#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
-
-void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
-{
- switch (port) {
- case FSL_DIU_PORT_DVI:
- clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
- PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
- break;
- case FSL_DIU_PORT_LVDS:
- clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
- PX_BRDCFG0_DLINK);
- break;
- case FSL_DIU_PORT_DLVDS:
- clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
- break;
- }
-}
-
-/**
- * mpc8610hpcd_set_pixel_clock: program the DIU's clock
- *
- * @pixclock: the wavelength, in picoseconds, of the clock
- */
-void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
-{
- struct device_node *guts_np = NULL;
- struct ccsr_guts __iomem *guts;
- unsigned long freq;
- u64 temp;
- u32 pxclk;
-
- /* Map the global utilities registers. */
- guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
- if (!guts_np) {
- pr_err("mpc8610hpcd: missing global utilities device node\n");
- return;
- }
-
- guts = of_iomap(guts_np, 0);
- of_node_put(guts_np);
- if (!guts) {
- pr_err("mpc8610hpcd: could not map global utilities device\n");
- return;
- }
-
- /* Convert pixclock from a wavelength to a frequency */
- temp = 1000000000000ULL;
- do_div(temp, pixclock);
- freq = temp;
-
- /*
- * 'pxclk' is the ratio of the platform clock to the pixel clock.
- * On the MPC8610, the value programmed into CLKDVDR is the ratio
- * minus one. The valid range of values is 2-31.
- */
- pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
- pxclk = clamp_t(u32, pxclk, 2, 31);
-
- /* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
-
- /* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
-
- iounmap(guts);
-}
-
-enum fsl_diu_monitor_port
-mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
-{
- return port;
-}
-
-#endif
-
-static void __init mpc86xx_hpcd_setup_arch(void)
-{
- struct resource r;
- unsigned char *pixis;
-
- if (ppc_md.progress)
- ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
-
- fsl_pci_assign_primary();
-
-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
- diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
- diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
- diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
- diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
- diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
-#endif
-
- pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
- if (pixis_node) {
- of_address_to_resource(pixis_node, 0, &r);
- of_node_put(pixis_node);
- pixis = ioremap(r.start, 32);
- if (!pixis) {
- printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
- return;
- }
- pixis_bdcfg0 = pixis + 8;
- pixis_arch = pixis + 1;
- } else
- printk(KERN_ERR "Err: "
- "can't find device node 'fsl,fpga-pixis'\n");
-
- printk("MPC86xx HPCD board from Freescale Semiconductor\n");
-}
-
-define_machine(mpc86xx_hpcd) {
- .name = "MPC86xx HPCD",
- .compatible = "fsl,MPC8610HPCD",
- .setup_arch = mpc86xx_hpcd_setup_arch,
- .init_IRQ = mpc86xx_init_irq,
- .get_irq = mpic_get_irq,
- .time_init = mpc86xx_time_init,
- .progress = udbg_progress,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-#endif
-};
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