MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option

Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e4198c5c2aa809a6bdba609a7041d78c705a7ba5..04a413d52b26afb97da22ff67c45be45e5394e68 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -890,6 +890,7 @@ config MACH_TX39XX
 
 config MACH_TX49XX
        bool "Toshiba TX49 series based machines"
+       select WAR_TX49XX_ICACHE_INDEX_INV
 
 config MIKROTIK_RB532
        bool "Mikrotik RB532 boards"
@@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP
 config WAR_R4600_V2_HIT_CACHEOP
        bool
 
+# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
+# the line which this instruction itself exists, the following
+# operation is not guaranteed."
+#
+# Workaround: do two phase flushing for Index_Invalidate_I
+config WAR_TX49XX_ICACHE_INDEX_INV
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 5826fbf4d3a2bb4d8c42b13932e77badac9748c4..1cb30485dc94b08a28d2fc7d75375bd537df7b1e 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 11b1f5e41af048936268645d3bfd07c0c8ae418d..79530836cc79325fea6a647dfb93c476b1e61f22 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index e47a7e186ed2785274812724ff86b3cef3d3b938..35286ba3ec5779f5409410c60c0239f3bafeda8f 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index f3c5cc8ff2bca310c391bcc22cc7156bd227c6bf..a18293c16ade6c3cf35946b716279ca5b707a0ef 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index f867697a179313822859a7eaee084b1af7e87333..1a6092e5c7b381631b99562bfa6a6c07ff14dadb 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index acda1ee3fb629642062f5d5cfd2ed16b73d4c4e5..031c7b9c52362b0fab248c4ba950c844667227bc 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,7 +7,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #ifdef CONFIG_CPU_R10000
 #define R10000_LLSC_WAR                        1

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ca381798f6ab7c2a777aa7ba84e6ba7ee809b324..25552158fa3a199bed7930c3610a3c91940c61e0 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d22ca4a3ec7233fa5bf166a0bee4f7b34f8331c5..9b0803537bcef998a612832aa0c25286c250747e 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index fccf25dcc26f519b172dd4e20cc13d8cf0c99a7e..924b51b9a3401c4c1037870addac00f29d724af8 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 556e0223e60b252793f1434cd9138e2cefd2433f..0536972b24c88c35bdf906a990e1853dffa45067 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 0e18f0753407226481430f9ef14160fa96ba647d..9e006fdcf38a396e04bed9e2a350c58d6427ab8b 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7019ddc4c68d87aedddca6bb55b01e9ae1cd739f..9293c5f9ffb2de35155c7ec9ebb668d43a7db30d 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define TX49XX_ICACHE_INDEX_INV_WAR    1
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 590bf2b16b33801d578968e5e1b773101cdafa0f..7a69641de57b594bee89f32bd610fcf28af6eff4 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,17 +93,6 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
- * the line which this instruction itself exists, the following
- * operation is not guaranteed."
- *
- * Workaround: do two phase flushing for Index_Invalidate_I
- */
-#ifndef TX49XX_ICACHE_INDEX_INV_WAR
-#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
-#endif
-
 /*
  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
  * opposes it being called that) where invalid instructions in the same

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index df09a3653c4f986ed0ef8deddaa16f22a7daf11b..4b12081f9843e7f32a96bc13d74f79dd8c3ed2f1 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -239,7 +239,7 @@ static void r4k_blast_dcache_setup(void)
                r4k_blast_dcache = blast_dcache128;
 }
 
-/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
+/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
 #define JUMP_TO_ALIGN(order) \
        __asm__ __volatile__( \
                "b\t1f\n\t" \
@@ -371,7 +371,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
                    cpu_is_r4600_v1_x())
                        r4k_blast_icache_page_indexed =
                                blast_icache32_r4600_v1_page_indexed;
-               else if (TX49XX_ICACHE_INDEX_INV_WAR)
+               else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
                        r4k_blast_icache_page_indexed =
                                tx49_blast_icache32_page_indexed;
                else if (current_cpu_type() == CPU_LOONGSON2EF)
@@ -399,7 +399,7 @@ static void r4k_blast_icache_setup(void)
                if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
                    cpu_is_r4600_v1_x())
                        r4k_blast_icache = blast_r4600_v1_icache32;
-               else if (TX49XX_ICACHE_INDEX_INV_WAR)
+               else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
                        r4k_blast_icache = tx49_blast_icache32;
                else if (current_cpu_type() == CPU_LOONGSON2EF)
                        r4k_blast_icache = loongson2_blast_icache32;