drm/amd/display: update GSP1 generic info packet for PSRSU
authorPo-Ting Chen <robin.chen@amd.com>
Fri, 26 Feb 2021 07:48:02 +0000 (15:48 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Apr 2023 12:50:21 +0000 (08:50 -0400)
Base on PSRSU specification, every seletive update frame need to use two
SDP to indicate the frame active range. So we occupy another GSP1 for
PSRSU execution.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Po-Ting Chen <robin.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c

index 9d08127d209b8e0e9b974ba31ae045311211bdd7..005dbe099a7a7f10e9bf15218a0a4ae13988e52e 100644 (file)
@@ -436,6 +436,21 @@ void enc3_stream_encoder_update_dp_info_packets(
                                &info_frame->vsc,
                                true);
        }
+       /* TODO: VSC SDP at packetIndex 1 should be retricted only if PSR-SU on.
+        * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
+        * In addition, currently the driver check the valid bit then update and
+        * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+        * while entering PSR-SU mode. So we need another parameter(e.g. send)
+        * in dc_info_packet to indicate which infopacket should be enabled by
+        * default here.
+        */
+       if (info_frame->vsc.valid) {
+               enc->vpg->funcs->update_generic_info_packet(
+                               enc->vpg,
+                               1,  /* packetIndex */
+                               &info_frame->vsc,
+                               true);
+       }
        /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
         * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
         * In addition, currently the driver check the valid bit then update and