iio: accel: adxl345: Move defines to header

Move defines from core to the header file. Keep the defines block together
in one location.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Link: https://lore.kernel.org/r/20240401194906.56810-4-l.rubusch@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h
index 284bd387ce69b001cd011842df4d0815e4c2d7ed..732820d34db3b73fdabd366dc2c76e41d25d64d4 100644 (file)
--- a/drivers/iio/accel/adxl345.h
+++ b/drivers/iio/accel/adxl345.h
@@ -8,6 +8,38 @@
 #ifndef _ADXL345_H_
 #define _ADXL345_H_
 
+#define ADXL345_REG_DEVID              0x00
+#define ADXL345_REG_OFSX               0x1E
+#define ADXL345_REG_OFSY               0x1F
+#define ADXL345_REG_OFSZ               0x20
+#define ADXL345_REG_OFS_AXIS(index)    (ADXL345_REG_OFSX + (index))
+#define ADXL345_REG_BW_RATE            0x2C
+#define ADXL345_REG_POWER_CTL          0x2D
+#define ADXL345_REG_DATA_FORMAT                0x31
+#define ADXL345_REG_DATAX0             0x32
+#define ADXL345_REG_DATAY0             0x34
+#define ADXL345_REG_DATAZ0             0x36
+#define ADXL345_REG_DATA_AXIS(index)   \
+       (ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
+
+#define ADXL345_BW_RATE                        GENMASK(3, 0)
+#define ADXL345_BASE_RATE_NANO_HZ      97656250LL
+
+#define ADXL345_POWER_CTL_MEASURE      BIT(3)
+#define ADXL345_POWER_CTL_STANDBY      0x00
+
+#define ADXL345_DATA_FORMAT_RANGE      GENMASK(1, 0)   /* Set the g range */
+#define ADXL345_DATA_FORMAT_JUSTIFY    BIT(2)  /* Left-justified (MSB) mode */
+#define ADXL345_DATA_FORMAT_FULL_RES   BIT(3)  /* Up to 13-bits resolution */
+#define ADXL345_DATA_FORMAT_SELF_TEST  BIT(7)  /* Enable a self test */
+
+#define ADXL345_DATA_FORMAT_2G         0
+#define ADXL345_DATA_FORMAT_4G         1
+#define ADXL345_DATA_FORMAT_8G         2
+#define ADXL345_DATA_FORMAT_16G                3
+
+#define ADXL345_DEVID                  0xE5
+
 /*
  * In full-resolution mode, scale factor is maintained at ~4 mg/LSB
  * in all g ranges.

diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
index e4afc6d2a681367962da58893fb9e090a5612467..f875a6275fb88b5df773b4fb98ee04509eb3be3a 100644 (file)
--- a/drivers/iio/accel/adxl345_core.c
+++ b/drivers/iio/accel/adxl345_core.c
@@ -17,38 +17,6 @@
 
 #include "adxl345.h"
 
-#define ADXL345_REG_DEVID              0x00
-#define ADXL345_REG_OFSX               0x1e
-#define ADXL345_REG_OFSY               0x1f
-#define ADXL345_REG_OFSZ               0x20
-#define ADXL345_REG_OFS_AXIS(index)    (ADXL345_REG_OFSX + (index))
-#define ADXL345_REG_BW_RATE            0x2C
-#define ADXL345_REG_POWER_CTL          0x2D
-#define ADXL345_REG_DATA_FORMAT                0x31
-#define ADXL345_REG_DATAX0             0x32
-#define ADXL345_REG_DATAY0             0x34
-#define ADXL345_REG_DATAZ0             0x36
-#define ADXL345_REG_DATA_AXIS(index)   \
-       (ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
-
-#define ADXL345_BW_RATE                        GENMASK(3, 0)
-#define ADXL345_BASE_RATE_NANO_HZ      97656250LL
-
-#define ADXL345_POWER_CTL_MEASURE      BIT(3)
-#define ADXL345_POWER_CTL_STANDBY      0x00
-
-#define ADXL345_DATA_FORMAT_RANGE      GENMASK(1, 0)   /* Set the g range */
-#define ADXL345_DATA_FORMAT_JUSTIFY    BIT(2)  /* Left-justified (MSB) mode */
-#define ADXL345_DATA_FORMAT_FULL_RES   BIT(3)  /* Up to 13-bits resolution */
-#define ADXL345_DATA_FORMAT_SELF_TEST  BIT(7)  /* Enable a self test */
-
-#define ADXL345_DATA_FORMAT_2G         0
-#define ADXL345_DATA_FORMAT_4G         1
-#define ADXL345_DATA_FORMAT_8G         2
-#define ADXL345_DATA_FORMAT_16G                3
-
-#define ADXL345_DEVID                  0xE5
-
 struct adxl345_data {
        const struct adxl345_chip_info *info;
        struct regmap *regmap;