drm/amdgpu/mes: correct register offset for sienna_cichlid

Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 8d2469fe2174f0971e0c5a07c238814f6d50fd7d..447bee159089655720c0b35ed54c092048d0cc7a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -31,6 +31,9 @@
 #include "v10_structs.h"
 #include "mes_api_def.h"
 
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid               0x2820
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX      1
+
 MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin");
 
@@ -490,15 +493,43 @@ static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);
 
        /* invalidate ICACHE */
-       data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+               break;
+       default:
+               data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+               break;
+       }
        data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
        data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
-       WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+               break;
+       default:
+               WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+               break;
+       }
 
        /* prime the ICACHE. */
-       data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+               break;
+       default:
+               data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+               break;
+       }
        data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
-       WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+               break;
+       default:
+               WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+               break;
+       }
 
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);