drm/amdgpu: correct ih cg programming for vega10 ih block

vega10/12 and RAVEN don't support soft override
ih_buffer_mem_clk.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 629ba46013aac3a5958313be5b4effc8b193a498..32c3dd0b62766c2bb112f5bb333386f03acfca47 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -640,15 +640,11 @@ static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
                def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
                field_val = enable ? 0 : 1;
                /**
-                * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE
-                * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
+                * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
                 */
-               if (adev->asic_type > CHIP_VEGA10) {
-                       data = REG_SET_FIELD(data, IH_CLK_CTRL,
-                                    IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
+               if (adev->asic_type == CHIP_RENOIR)
                        data = REG_SET_FIELD(data, IH_CLK_CTRL,
                                     IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
-               }
 
                data = REG_SET_FIELD(data, IH_CLK_CTRL,
                                     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);