arm64: dts: mt8192: Add pwrap node

Add pwrap node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220318144534.17996-2-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb2946134ba70c63748ae699ec9e4b4473b1..76428599444eb04ebf3bf7c8388adb6af578a81f 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
                        clock-names = "clk13m";
                };
 
+               pwrap: pwrap@10026000 {
+                       compatible = "mediatek,mt6873-pwrap";
+                       reg = <0 0x10026000 0 0x1000>;
+                       reg-names = "pwrap";
+                       interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+                                <&infracfg CLK_INFRA_PMIC_TMR>;
+                       clock-names = "spi", "wrap";
+                       assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+               };
+
                scp_adsp: clock-controller@10720000 {
                        compatible = "mediatek,mt8192-scp_adsp";
                        reg = <0 0x10720000 0 0x1000>;