For MT8188, VPPSYS0 and VPPSYS1 are 2 display pipes with
hardware differences in power domains, clocks and subsystem counts,
which should be probed from mtk-mmsys driver to populate device by
platform_device_register_data then start its own clock driver.
Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
+ - mediatek,mt8188-vppsys0
+ - mediatek,mt8188-vppsys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
- mediatek,mt8188-vdecsys
- mediatek,mt8188-vdecsys-soc
- mediatek,mt8188-vencsys
- - mediatek,mt8188-vppsys0
- - mediatek,mt8188-vppsys1
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0