mwifiex: support for event done interrupt

This patch adds support for writing CPU event interrupt done back
to device.
Patch also increases interrupt buffer ring size from 4 to 8.

Signed-off-by: Avinash Patil <patila@marvell.com>
Signed-off-by: Cathy Luo <cluo@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/mwifiex/pcie.c b/drivers/net/wireless/mwifiex/pcie.c
index 27c2bf86070927165c6da2b75580835d908e80e4..2ada1b709778e393651d704c7dfb890e02203495 100644 (file)
--- a/drivers/net/wireless/mwifiex/pcie.c
+++ b/drivers/net/wireless/mwifiex/pcie.c
@@ -1726,6 +1726,13 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
                   buffer is released. This is just to make things simpler,
                   we need to find a better method of managing these buffers.
                */
+       } else {
+               if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
+                                     CPU_INTR_EVENT_DONE)) {
+                       dev_warn(adapter->dev,
+                                "Write register failed\n");
+                       return -1;
+               }
        }
 
        return 0;

diff --git a/drivers/net/wireless/mwifiex/pcie.h b/drivers/net/wireless/mwifiex/pcie.h
index a1a8fd3bc1be5355289b34457cb4ff1cafe894ba..200e8b0cb5824e565ee0eda1c21055d7940be755 100644 (file)
--- a/drivers/net/wireless/mwifiex/pcie.h
+++ b/drivers/net/wireless/mwifiex/pcie.h
@@ -40,8 +40,8 @@
 #define MWIFIEX_TXBD_MASK                      0x3F
 #define MWIFIEX_RXBD_MASK                      0x3F
 
-#define MWIFIEX_MAX_EVT_BD                     0x04
-#define MWIFIEX_EVTBD_MASK                     0x07
+#define MWIFIEX_MAX_EVT_BD                     0x08
+#define MWIFIEX_EVTBD_MASK                     0x0f
 
 /* PCIE INTERNAL REGISTERS */
 #define PCIE_SCRATCH_0_REG                             0xC10
@@ -69,6 +69,7 @@
 #define CPU_INTR_DOOR_BELL                             BIT(1)
 #define CPU_INTR_SLEEP_CFM_DONE                        BIT(2)
 #define CPU_INTR_RESET                                 BIT(3)
+#define CPU_INTR_EVENT_DONE                            BIT(5)
 
 #define HOST_INTR_DNLD_DONE                            BIT(0)
 #define HOST_INTR_UPLD_RDY                             BIT(1)