&constraints_rates);
 
        machine->i2s_instance = I2S_SP_INSTANCE;
+       machine->capture_channel = CAP_CHANNEL1;
        return da7219_clk_enable(substream);
 }
 
        da7219_clk_disable();
 }
 
-static int cz_dmic_startup(struct snd_pcm_substream *substream)
+static int cz_dmic0_startup(struct snd_pcm_substream *substream)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct snd_soc_card *card = rtd->card;
        return da7219_clk_enable(substream);
 }
 
+static int cz_dmic1_startup(struct snd_pcm_substream *substream)
+{
+       struct snd_soc_pcm_runtime *rtd = substream->private_data;
+       struct snd_soc_card *card = rtd->card;
+       struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
+
+       machine->i2s_instance = I2S_SP_INSTANCE;
+       machine->capture_channel = CAP_CHANNEL0;
+       return da7219_clk_enable(substream);
+}
+
 static void cz_dmic_shutdown(struct snd_pcm_substream *substream)
 {
        da7219_clk_disable();
        .shutdown = cz_max_shutdown,
 };
 
-static const struct snd_soc_ops cz_dmic_cap_ops = {
-       .startup = cz_dmic_startup,
+static const struct snd_soc_ops cz_dmic0_cap_ops = {
+       .startup = cz_dmic0_startup,
+       .shutdown = cz_dmic_shutdown,
+};
+
+static const struct snd_soc_ops cz_dmic1_cap_ops = {
+       .startup = cz_dmic1_startup,
        .shutdown = cz_dmic_shutdown,
 };
 
                .ops = &cz_max_play_ops,
        },
        {
-               .name = "dmic",
-               .stream_name = "DMIC Capture",
+               /* C panel DMIC */
+               .name = "dmic0",
+               .stream_name = "DMIC0 Capture",
                .platform_name = "acp_audio_dma.0.auto",
                .cpu_dai_name = "designware-i2s.3.auto",
                .codec_dai_name = "adau7002-hifi",
                .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
                                | SND_SOC_DAIFMT_CBM_CFM,
                .dpcm_capture = 1,
-               .ops = &cz_dmic_cap_ops,
+               .ops = &cz_dmic0_cap_ops,
+       },
+       {
+               /* A/B panel DMIC */
+               .name = "dmic1",
+               .stream_name = "DMIC1 Capture",
+               .platform_name = "acp_audio_dma.0.auto",
+               .cpu_dai_name = "designware-i2s.2.auto",
+               .codec_dai_name = "adau7002-hifi",
+               .codec_name = "ADAU7002:00",
+               .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
+                               | SND_SOC_DAIFMT_CBM_CFM,
+               .dpcm_capture = 1,
+               .ops = &cz_dmic1_cap_ops,
        },
 };
 
 
                                       rtd->dma_dscr_idx_2, asic_type);
 }
 
+static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
+                                      u16 cap_channel)
+{
+       u32 val, ch_reg, imr_reg, res_reg;
+
+       switch (cap_channel) {
+       case CAP_CHANNEL1:
+               ch_reg = mmACP_I2SMICSP_RER1;
+               res_reg = mmACP_I2SMICSP_RCR1;
+               imr_reg = mmACP_I2SMICSP_IMR1;
+               break;
+       case CAP_CHANNEL0:
+       default:
+               ch_reg = mmACP_I2SMICSP_RER0;
+               res_reg = mmACP_I2SMICSP_RCR0;
+               imr_reg = mmACP_I2SMICSP_IMR0;
+               break;
+       }
+       val = acp_reg_read(acp_mmio,
+                          mmACP_I2S_16BIT_RESOLUTION_EN);
+       if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
+               acp_reg_write(0x0, acp_mmio, ch_reg);
+               /* Set 16bit resolution on capture */
+               acp_reg_write(0x2, acp_mmio, res_reg);
+       }
+       val = acp_reg_read(acp_mmio, imr_reg);
+       val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
+       val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
+       acp_reg_write(val, acp_mmio, imr_reg);
+       acp_reg_write(0x1, acp_mmio, ch_reg);
+}
+
+static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
+                                       u16 cap_channel)
+{
+       u32 val, ch_reg, imr_reg;
+
+       switch (cap_channel) {
+       case CAP_CHANNEL1:
+               imr_reg = mmACP_I2SMICSP_IMR1;
+               ch_reg = mmACP_I2SMICSP_RER1;
+               break;
+       case CAP_CHANNEL0:
+       default:
+               imr_reg = mmACP_I2SMICSP_IMR0;
+               ch_reg = mmACP_I2SMICSP_RER0;
+               break;
+       }
+       val = acp_reg_read(acp_mmio, imr_reg);
+       val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
+       val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
+       acp_reg_write(val, acp_mmio, imr_reg);
+       acp_reg_write(0x0, acp_mmio, ch_reg);
+}
+
 /* Start a given DMA channel transfer */
 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num)
 {
        if (WARN_ON(!rtd))
                return -EINVAL;
 
-       if (pinfo)
+       if (pinfo) {
                rtd->i2s_instance = pinfo->i2s_instance;
+               rtd->capture_channel = pinfo->capture_channel;
+       }
        if (adata->asic_type == CHIP_STONEY) {
                val = acp_reg_read(adata->acp_mmio,
                                   mmACP_I2S_16BIT_RESOLUTION_EN);
                        acp_dma_start(rtd->acp_mmio, rtd->ch1);
                        acp_dma_start(rtd->acp_mmio, rtd->ch2);
                } else {
+                       if (rtd->capture_channel == CAP_CHANNEL0) {
+                               acp_dma_cap_channel_disable(rtd->acp_mmio,
+                                                           CAP_CHANNEL1);
+                               acp_dma_cap_channel_enable(rtd->acp_mmio,
+                                                          CAP_CHANNEL0);
+                       }
+                       if (rtd->capture_channel == CAP_CHANNEL1) {
+                               acp_dma_cap_channel_disable(rtd->acp_mmio,
+                                                           CAP_CHANNEL0);
+                               acp_dma_cap_channel_enable(rtd->acp_mmio,
+                                                          CAP_CHANNEL1);
+                       }
                        acp_dma_start(rtd->acp_mmio, rtd->ch2);
                        acp_dma_start(rtd->acp_mmio, rtd->ch1);
                }