soc: mediatek: Add MT8188 VDOSYS reset bit map

Add MT8188 reset bit map for VDOSYS0 and VDOSYS1.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index a9490c3c42560f6b7badf5ea92b104d5d426fea9..6bebf1a69fc0763e9c4835c98114fe3fb3058b82 100644 (file)
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -3,6 +3,10 @@
 #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
 #define __SOC_MEDIATEK_MT8188_MMSYS_H
 
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B                          0x190
 #define MT8188_VDO0_OVL_MOUT_EN                                0xf14
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0            BIT(0)
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0            BIT(1)
@@ -67,6 +71,7 @@
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE         BIT(18)
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0                BIT(19)
 
+#define MT8188_VDO1_SW0_RST_B                                  0x1d0
 #define MT8188_VDO1_HDR_TOP_CFG                                        0xd00
 #define MT8188_VDO1_MIXER_IN1_ALPHA                            0xd30
 #define MT8188_VDO1_MIXER_IN1_PAD                              0xd40
@@ -117,6 +122,85 @@
 #define MT8188_VDO1_MIXER_SOUT_SEL_IN                          0xf68
 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER               0
 
+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+       [MT8188_VDO0_RST_DISP_OVL0]     = MMSYS_RST_NR(0, 0),
+       [MT8188_VDO0_RST_FAKE_ENG0]     = MMSYS_RST_NR(0, 2),
+       [MT8188_VDO0_RST_DISP_CCORR0]   = MMSYS_RST_NR(0, 4),
+       [MT8188_VDO0_RST_DISP_MUTEX0]   = MMSYS_RST_NR(0, 6),
+       [MT8188_VDO0_RST_DISP_GAMMA0]   = MMSYS_RST_NR(0, 8),
+       [MT8188_VDO0_RST_DISP_DITHER0]  = MMSYS_RST_NR(0, 10),
+       [MT8188_VDO0_RST_DISP_WDMA0]    = MMSYS_RST_NR(0, 17),
+       [MT8188_VDO0_RST_DISP_RDMA0]    = MMSYS_RST_NR(0, 19),
+       [MT8188_VDO0_RST_DSI0]          = MMSYS_RST_NR(0, 21),
+       [MT8188_VDO0_RST_DSI1]          = MMSYS_RST_NR(0, 22),
+       [MT8188_VDO0_RST_DSC_WRAP0]     = MMSYS_RST_NR(0, 23),
+       [MT8188_VDO0_RST_VPP_MERGE0]    = MMSYS_RST_NR(0, 24),
+       [MT8188_VDO0_RST_DP_INTF0]      = MMSYS_RST_NR(0, 25),
+       [MT8188_VDO0_RST_DISP_AAL0]     = MMSYS_RST_NR(0, 26),
+       [MT8188_VDO0_RST_INLINEROT0]    = MMSYS_RST_NR(0, 27),
+       [MT8188_VDO0_RST_APB_BUS]       = MMSYS_RST_NR(0, 28),
+       [MT8188_VDO0_RST_DISP_COLOR0]   = MMSYS_RST_NR(0, 29),
+       [MT8188_VDO0_RST_MDP_WROT0]     = MMSYS_RST_NR(0, 30),
+       [MT8188_VDO0_RST_DISP_RSZ0]     = MMSYS_RST_NR(0, 31),
+};
+
+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+       [MT8188_VDO1_RST_SMI_LARB2]                     = MMSYS_RST_NR(0, 0),
+       [MT8188_VDO1_RST_SMI_LARB3]                     = MMSYS_RST_NR(0, 1),
+       [MT8188_VDO1_RST_GALS]                          = MMSYS_RST_NR(0, 2),
+       [MT8188_VDO1_RST_FAKE_ENG0]                     = MMSYS_RST_NR(0, 3),
+       [MT8188_VDO1_RST_FAKE_ENG1]                     = MMSYS_RST_NR(0, 4),
+       [MT8188_VDO1_RST_MDP_RDMA0]                     = MMSYS_RST_NR(0, 5),
+       [MT8188_VDO1_RST_MDP_RDMA1]                     = MMSYS_RST_NR(0, 6),
+       [MT8188_VDO1_RST_MDP_RDMA2]                     = MMSYS_RST_NR(0, 7),
+       [MT8188_VDO1_RST_MDP_RDMA3]                     = MMSYS_RST_NR(0, 8),
+       [MT8188_VDO1_RST_VPP_MERGE0]                    = MMSYS_RST_NR(0, 9),
+       [MT8188_VDO1_RST_VPP_MERGE1]                    = MMSYS_RST_NR(0, 10),
+       [MT8188_VDO1_RST_VPP_MERGE2]                    = MMSYS_RST_NR(0, 11),
+       [MT8188_VDO1_RST_VPP_MERGE3]                    = MMSYS_RST_NR(1, 0),
+       [MT8188_VDO1_RST_VPP_MERGE4]                    = MMSYS_RST_NR(1, 1),
+       [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC]         = MMSYS_RST_NR(1, 2),
+       [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC]         = MMSYS_RST_NR(1, 3),
+       [MT8188_VDO1_RST_DISP_MUTEX]                    = MMSYS_RST_NR(1, 4),
+       [MT8188_VDO1_RST_MDP_RDMA4]                     = MMSYS_RST_NR(1, 5),
+       [MT8188_VDO1_RST_MDP_RDMA5]                     = MMSYS_RST_NR(1, 6),
+       [MT8188_VDO1_RST_MDP_RDMA6]                     = MMSYS_RST_NR(1, 7),
+       [MT8188_VDO1_RST_MDP_RDMA7]                     = MMSYS_RST_NR(1, 8),
+       [MT8188_VDO1_RST_DP_INTF1_MMCK]                 = MMSYS_RST_NR(1, 9),
+       [MT8188_VDO1_RST_DPI0_MM_CK]                    = MMSYS_RST_NR(1, 10),
+       [MT8188_VDO1_RST_DPI1_MM_CK]                    = MMSYS_RST_NR(1, 11),
+       [MT8188_VDO1_RST_MERGE0_DL_ASYNC]               = MMSYS_RST_NR(1, 13),
+       [MT8188_VDO1_RST_MERGE1_DL_ASYNC]               = MMSYS_RST_NR(1, 14),
+       [MT8188_VDO1_RST_MERGE2_DL_ASYNC]               = MMSYS_RST_NR(1, 15),
+       [MT8188_VDO1_RST_MERGE3_DL_ASYNC]               = MMSYS_RST_NR(1, 16),
+       [MT8188_VDO1_RST_MERGE4_DL_ASYNC]               = MMSYS_RST_NR(1, 17),
+       [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC]     = MMSYS_RST_NR(1, 18),
+       [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC]   = MMSYS_RST_NR(1, 19),
+       [MT8188_VDO1_RST_PADDING0]                      = MMSYS_RST_NR(1, 20),
+       [MT8188_VDO1_RST_PADDING1]                      = MMSYS_RST_NR(1, 21),
+       [MT8188_VDO1_RST_PADDING2]                      = MMSYS_RST_NR(1, 22),
+       [MT8188_VDO1_RST_PADDING3]                      = MMSYS_RST_NR(1, 23),
+       [MT8188_VDO1_RST_PADDING4]                      = MMSYS_RST_NR(1, 24),
+       [MT8188_VDO1_RST_PADDING5]                      = MMSYS_RST_NR(1, 25),
+       [MT8188_VDO1_RST_PADDING6]                      = MMSYS_RST_NR(1, 26),
+       [MT8188_VDO1_RST_PADDING7]                      = MMSYS_RST_NR(1, 27),
+       [MT8188_VDO1_RST_DISP_RSZ0]                     = MMSYS_RST_NR(1, 28),
+       [MT8188_VDO1_RST_DISP_RSZ1]                     = MMSYS_RST_NR(1, 29),
+       [MT8188_VDO1_RST_DISP_RSZ2]                     = MMSYS_RST_NR(1, 30),
+       [MT8188_VDO1_RST_DISP_RSZ3]                     = MMSYS_RST_NR(1, 31),
+       [MT8188_VDO1_RST_HDR_VDO_FE0]                   = MMSYS_RST_NR(2, 0),
+       [MT8188_VDO1_RST_HDR_GFX_FE0]                   = MMSYS_RST_NR(2, 1),
+       [MT8188_VDO1_RST_HDR_VDO_BE]                    = MMSYS_RST_NR(2, 2),
+       [MT8188_VDO1_RST_HDR_VDO_FE1]                   = MMSYS_RST_NR(2, 16),
+       [MT8188_VDO1_RST_HDR_GFX_FE1]                   = MMSYS_RST_NR(2, 17),
+       [MT8188_VDO1_RST_DISP_MIXER]                    = MMSYS_RST_NR(2, 18),
+       [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC]          = MMSYS_RST_NR(2, 19),
+       [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC]          = MMSYS_RST_NR(2, 20),
+       [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC]          = MMSYS_RST_NR(2, 21),
+       [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC]          = MMSYS_RST_NR(2, 22),
+       [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC]           = MMSYS_RST_NR(2, 23),
+};
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
        {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index ae8d7076c42c164b8407b47e3c4d4a92b3bf0d87..f370f4ec4b88860036c34babd022ad85693c22a5 100644 (file)
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
        .clk_driver = "clk-mt8188-vdo0",
        .routes = mmsys_mt8188_routing_table,
        .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+       .sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+       .rst_tb = mmsys_mt8188_vdo0_rst_tb,
+       .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
 };
 
 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
        .clk_driver = "clk-mt8188-vdo1",
        .routes = mmsys_mt8188_vdo1_routing_table,
        .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
-       .num_resets = 96,
+       .sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+       .rst_tb = mmsys_mt8188_vdo1_rst_tb,
+       .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
        .vsync_len = 1,
 };