drm/i915/icl: Define register for DSI PLL

This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.

v2: Review comments from Jani N
    - Fix spaces while defining ICL_ESC_CLK_DIV_MASK
    - Define shift and mask for bitfields.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530795727-28644-2-git-send-email-madhav.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 097000520a80f1d84446f399b585fc4f5464d3e4..dc953ee7e3b3a72c5912f756444332cf1c33b520 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9538,6 +9538,21 @@ enum skl_power_gate {
 #define MIPIO_TXESC_CLK_DIV2                   _MMIO(0x160008)
 #define  GLK_TX_ESC_CLK_DIV2_MASK                      0x3FF
 
+#define _ICL_DSI_ESC_CLK_DIV0          0x6b090
+#define _ICL_DSI_ESC_CLK_DIV1          0x6b890
+#define ICL_DSI_ESC_CLK_DIV(port)      _MMIO_PORT((port),      \
+                                                       _ICL_DSI_ESC_CLK_DIV0, \
+                                                       _ICL_DSI_ESC_CLK_DIV1)
+#define _ICL_DPHY_ESC_CLK_DIV0         0x162190
+#define _ICL_DPHY_ESC_CLK_DIV1         0x6C190
+#define ICL_DPHY_ESC_CLK_DIV(port)     _MMIO_PORT((port),      \
+                                               _ICL_DPHY_ESC_CLK_DIV0, \
+                                               _ICL_DPHY_ESC_CLK_DIV1)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_MASK         (0x1f << 16)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT        16
+#define  ICL_ESC_CLK_DIV_MASK                  0x1ff
+#define  ICL_ESC_CLK_DIV_SHIFT                 0
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP         _MMIO(0x2358)
 #define ILK_TIMESTAMP_HI       _MMIO(0x70070)